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參數(shù)資料
| 型號： | IDT82P2288BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 325/362頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 8CHAN 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2346 82P2288BB IDT82P2288BB-ND |
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
65
March 04, 2009
3.14 ELASTIC STORE BUFFER
In Receive Clock Slave mode and Receive Multiplexed mode, a 2-
basic-frame depth Elastic Store Buffer is used to synchronize the
incoming frames to the (Multiplexed) Receive Side System Clock
derived from the RSCKn/MRSCK pin, and to the (Multiplexed) Receive
Side System Frame Pulse derived from the RSFSn/MRSFS pin. A write
pointer is used to write the data to the Elastic Store Buffer, while a read
pointer is used to read the data from the Elastic Store Buffer.
When the average frequency of the incoming data is greater than the
average frequency of the (Multiplexed) Receive Side System Clock
(RSCKn/MRSCK), the write pointer will be faster than the read pointer
and the Elastic Store Buffer will be filled. Until there is less than or equal
to 2 bytes between the write pointer and the read pointer, a frame will be
deleted after its prior frame is read. When the read pointer crosses the
frame boundary, a controlled slip will occur with a ‘1’ indicated in the
SLIPD bit.
When the average frequency of the incoming data is less than the
average frequency of the RSCKn/MRSCK, the write pointer will be
slower than the read pointer and the Elastic Store Buffer will be empty.
Until there is less than or equal to 2 bytes between the write pointer and
the read pointer, the frame will be repeated after it is read. When the
read pointer crosses the next frame boundary, a controlled slip will occur
with a ‘0’ indicated in the SLIPD bit.
When the slip occurs, the SLIPI bit will indicate it. An interrupt on the
INT pin will occur if the SLIPE bit is ‘1’.
In Receive Clock Slave mode and Receive Multiplexed mode, if it is
out of synchronization, the trunk code programmed in the
TRKCODE[7:0] bits will be set to replace the data if the TRKEN bit is set
to ‘1’.
In Receive Clock Master mode, the Elastic Store Buffer is bypassed
unless the device is in the Payload Loopback diagnosis mode (refer to
3.15 RECEIVE CAS/RBS BUFFER
The Receive CAS/RBS Buffer extracts the signaling bits from the
received data stream.
3.15.1 T1/J1 MODE
In SF/ESF/SLC-96 format, the signaling bits are located in the Bit 8
of Frame 6n (n = 1,2 in SF format; 1
≤ n ≤ 4 in ESF format; 1 ≤ n ≤ 12 in
The signaling codewords (AB or ABCD) are clocked out on the RSIGn/
MRSIGA(MRSIGB) pins. They are in the lower nibble of the channel with
its corresponding data serializing on the RSDn/MRSDA(MRSIGB) pins
(as shown in Figure 16).
When the EXTRACT bit is set to ‘1’, the signaling bits in its corre-
sponding channel are extracted to the A,B,C,D bits in the Extracted
Signaling Data/Extract Enable register. In SF format, the C,D bits in the
register are the repetition of the signaling bits A,B. The data in the
A,B,C,D bits in the Extracted Signaling Data/Extract Enable register are
the data to be output on the RSIGn/MRSIGA(MRSIGB) pins. However,
in T1-DM format, there is no signaling bits.
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received AB/ABCD codewords
of the same channel are identical.
Signaling freezing is performed automatically when it is out of frame
synchronization or when slips occurs in the Elastic Store Buffer. It is also
performed when the FREEZE bit is set to ‘1’. The signaling freezing
freezes the signaling data in the A,B,C,D bits in the Extracted Signaling
Data/Extract Enable register as the previous valid value.
In the ESF and SLC-96 format, if the SIGF bit is set to ‘0’, the
extracted signaling bits are in 4 states signaling, i.e., the signaling bits
on Framer 6 & 18 of a signaling multi-frame are recognized as ‘A’ and
the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the
signaling bits A & B will be saved in the Extracted Signaling Data/Extract
Enable register, and the C & D bits in the Extracted Signaling Data/
Extract Enable register are Don’t-Care. If the SIGF bit is set to ‘1’, the
extracted signaling bits are in 16 states signaling, i.e., four signaling bits
A, B, C & D are all saved in the Extracted Signaling Data/Extract Enable
register.
Each time the extracted signaling bits stored in the Extracted
Signaling Data/Extract Enable register are changed, it is captured by the
corresponding COSI[X] bit (1
≤ X ≤ 24). When the SIGE bit is set to ‘1’,
any one of the COSI[X] bits being ‘1’ will generate an interrupt and will
be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers of
the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
Table 34: Related Bit / Register In Chapter 3.14
Bit
Register
Address (Hex)
SLIPD
ELST Configuration
07C, 17C, 27C, 37C,
47C, 57C, 67C, 77C
SLIPE
TRKEN
SLIPI
ELST Interrupt Indication
07D, 17D, 27D, 37D,
47D, 57D, 67D, 77D
TRKCODE[7:0]
ELST Trunk Code
07E, 17E, 27E, 37E,
47E, 57E, 67E, 77E
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| IDT82P2288BB8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Octal T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2288BBG | 功能描述:TXRX OCTAL T1/E1/J1 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2288BBG8 | 功能描述:TXRX T1/J1/E1 8CHAN 256-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2521 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit |
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