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參數(shù)資料
| 型號： | IDT82P2288BBG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 305/362頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 8CHAN 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82P2288BBG8 |
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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
47
March 04, 2009
3.8.2.2 Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor keeps on
monitoring the received data stream to detect errors and judge if it is out
of synchronization.
The following ten kinds of errors are detected:
FAS/NFAS Bit/Pattern Error: The criteria of this error are deter-
mined by the WORDERR bit and the CNTNFAS bit (refer to
Table 19). This error event is captured by the FERI bit and is for-
warded to the Performance Monitor.
CRC Multi-Frame Alignment Pattern Error: The received CRC
Multi-Frame alignment signals are compared with the expected
ones (‘001011’). When one or more bits do not match, a single
CRC Multi-Frame alignment pattern error event is generated. This
error event is captured by the CMFERI bit.
CRC-4 Error: When the local calculated CRC-4 of the current
received CRC Sub Multi-Frame does not match the received CRC-
4 of the next received CRC Sub Multi-Frame, a single CRC-4 error
event is generated. This error event is captured by the CRCEI bit
and is forwarded to the Performance Monitor.
Excessive CRC-4 Error: Once the accumulated CRC-4 errors are
not less than 915 occasions (915 is included) in a 1 second fixed
window, an excessive CRC-4 error event is generated. This error
event is captured by the EXCRCERI bit.
CAS Signaling Multi-Frame Alignment Pattern Error: The received
Signaling Multi-Frame alignment signals are compared with the
expected ones (‘0000’). When one or more bits do not match, a
single CAS Signaling Multi-Frame alignment pattern error event is
generated. This error event is captured by the SMFERI bit.
Far End Block Error (FEBE): When any of the CRC error indication
(E1 or E2) bits is received as a logic 0, a far end block error event
is generated. This error event is captured by the FEBEI bit and is
forwarded to the Performance Monitor.
Continuous RAI & FEBE Error: When a logic 1 is received in the A
bit and a logic 0 is received in any of the E1 or E2 bit for 10 ms, the
RAICRCV bit is set. This bit is cleared if any of the conditions is not
met.
Continuous FEBE Error: When a logic 0 is received in any of the
E1 or E2 bits on
≥ 990 occasions per second for the latest 5 con-
secutive seconds, the CFEBEV bit is set, otherwise this bit will be
cleared.
NT FEBE Error (per ETS 300 233): If the 4-bit Sa6 codeword of a
CRC Sub Multi-Frame is matched with ‘0001’ or ‘0011’, the Net-
work Terminal Far End Block Error event is generated. This error
event is captured by the TFEBEI bit and is forwarded to the Perfor-
mance Monitor.
NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of a
CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Net-
work Terminal CRC Error event is generated. This error event is
captured by the TCRCEI bit and is forwarded to the Performance
Monitor.
Various errors will lead to out of synchronization:
Out Of Basic Frame Synchronization
If there is one or more bit errors in a FAS pattern, a FAS pattern error
will occur. If the NFAS bit position is received as zero, a NFAS error will
occur. Determined by the BIT2C bit, if this bit is ‘0’, 3 consecutive FAS
pattern errors lead to out of Basic frame synchronization; if this bit is ‘1’,
3 consecutive FAS pattern errors or 3 consecutive NFAS errors lead to
out of Basic frame synchronization. Then if the REFEN bit is ‘1’, the
Frame Processor will start to search for synchronization again. Addition-
ally, Excessive CRC-4 Error also leads to out of Basic frame synchroni-
zation. In this condition, both the REFEN bit being ‘1’ and the REFCRCE
bit being ‘1’ will allow the Frame Processor to search for synchronization
again. If the REFEN bit is ‘0’, no error can lead to reframe except for
manually setting. The manual reframe searches from Basic frame and is
executed by a transition from ‘0’ to ‘1’ on the REFR bit. During out of
Basic frame synchronization state, the FAS/NFAS Bit/Pattern Error
detection is suspended.
Once resynchronized, if the new-found Basic frame alignment
pattern position differs from the previous one, the change of frame align-
ment event is generated. This event is captured by the COFAI bit and is
forwarded to the Performance Monitor.
Out Of CRC Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CRC Multi-Frame synchronization. During out of CRC
Multi-Frame synchronization state, the FAS/NFAS Bit/Pattern Error
detection, CRC Multi-Frame Alignment Pattern Error detection, CRC-4
Error detection, Excessive CRC-4 Error detection, Far End Block Error
detection, Continuous RAI & FEBE Error detection, Continuous FEBE
Error detection, NT CRC Error detection and NT FEBE Error detection
are suspended.
Out Of CAS Signaling Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CAS Signaling Multi-Frame synchronization.
In addition, determined by the SMFASC bit and the TS16C bit, if the
CAS Signaling Multi-Frame Alignment Pattern Error occurs or all the
contents in TS16 are zeros, it is out of CAS Signaling Multi-Frame
synchronization. Then no matter what the value in the REFEN bit is, the
Frame Processor will search for the CAS Signaling Multi-Frame
Table 19: FAS/NFAS Bit/Pattern Error Criteria
WORDER
R
CNTNFA
S
Error Generation
0
Each bit error in FAS is counted as an error event.
1
0
A FAS pattern error is counted as an error event.
0
1
Each bit error in FAS or NFAS error is counted as
an error event.
1
A FAS pattern error or NFAS error is counted as an
error event.
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