參數(shù)資料
型號: IDT82V2051EPP
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/61頁
文件大?。?/td> 0K
描述: IC LIU E1 SGL SHORT HAUL 44-TQFP
標準包裝: 80
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
其它名稱: 82V2051EPP
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Pin Description
10
December 9, 2005
MCLK
I
9
MCLK: Master Clock input
A built-in clock system that accepts a 2.048MHz reference clock. This reference clock is used to generate several internal ref-
erence signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition.
Reference clock to transmit All Ones, all zeros and PRBS pattern. Note that for ATAO and AIS, MCLK is always used as
the reference clock.
Reference clock during the Transmit All Ones (TAO) condition or sending PRBS in hardware control mode.
The loss of MCLK will turn TTIP/TRING into high impedance status.
LOS
O
7
LOS: Loss of Signal Output
This is an active high signal used to indicate the loss of received signal. When LOS pin becomes high, it indicates the loss of
received signal. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss
of signal are described in 3.5 Los And AIS Detection.
REF
I
43
REF: reference resister
An external resistor (3 K
, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
MODE1
MODE0
I17
16
MODE[1:0]: operation mode of Control interface select
The level on this pin determines which control mode is used to control the device as follows:
The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
The parallel multiplexed microcontroller interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and
INT pins. (refer to 3.11 Microcontroller Interfaces for details)
Hardware interface consists of PULS, THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, RPD, MODE[1:0] and
RXTXM[1:0]
RCLKE
I
11
RCLKE: the active edge of RCLK select
In hardware control mode, this pin selects the active edge of RCLK
L= select the rising edge as the active edge of RCLK
H= select the falling edge as the active edge of RCLK
In software control mode, this pin should be connected to GNDIO.
CS
RXTXM1
I21
CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial or
parallel microcontroller interface.
RXTXM[1:0]: Receive and transmit path operation mode select
In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3 line
coding:
00= single rail with HDB3 coding
01= single rail with AMI coding
10= dual rail interface with CDR enabled
11= slicer mode (dual rail interface with CDR disabled)
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
MODE[1:0]
Control Interface mode
00
Hardware interface
01
Serial Microcontroller Interface
10
Parallel –Multiplexed -Motorola Interface
11
Parallel –Multiplexed -Intel Interface
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