Figure-5 Receive Path Function Block Diagram" />
參數(shù)資料
型號： IDT82V2052EPF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 14/70頁
文件大?。?/td> 0K
描述： IC LIU E1 2CH SHORT HAUL 80-TQFP
標準包裝： 45
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-TQFP（14x14）
包裝： 托盤
其它名稱： 82V2052EPF
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
21
December 12, 2005
Figure-5 Receive Path Function Block Diagram
Figure-6 Transmit/Receive Line Circuit
In hardware control mode, TERMn, PULSn pins can be used to select
impedance matching for both receiver and transmitter on a per channel
basis. If TERMn pin is low, internal impedance network will be used. If
TERMnpinishigh,externalimpedancenetworkwillbeused.Wheninternal
impedance network is used, PULSn pins should be set to select specific
internal impedance for the corresponding channel. Refer to 5 HARDWARE
for details.
3.3.2
LINE MONITOR
The non-intrusive monitoring on channels located in other chips can be
performed by tapping the monitored channel through a high impedance
bridging circuit. Refer to Figure-7 and Figure-8.
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor
Gain should be set to 0 dB.
In hardware control mode, MONTn pin can be used to set the Monitor
Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for
the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for
the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUM-
for details.
Table-5 Impedance Matching for Receiver
Cable Configuration
Internal Termination
External Termination
R_TERM[2:0]
RR
R_TERM[2:0]
RR
E1 / 75
000
120
1XX
75
E1 / 120
001
120
Monitor Gain/
Adaptive Equalizer
LOS/AIS
Detector
Data Slicer
Decoder
LOS
RCLK
RDP
RDN
RTIP
Clock
and Data
Recovery
Receive
Internal
termination
RRING
Jitter
Attenuator
Note:
1. Common decoupling capacitor. One per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. RT/ RR: refer to Table-4 and Table-5 respecivley for RT and RR values
A
B
RX Line
RR4
TX Line
RT4
RTIPn
RRINGn
TRINGn
TTIPn
0.1
F
GNDTn
VDDTn
IDT
82V2052E
VDDTn
D4
D3
D2
D1
1:1
2:1
68
F1
D6
D5
D8
D7
Cp
VDDRn
One of the Two Identical Channels
2
3
3.3 V
0.1
F
GNDRn
VDDRn
68
F
3.3 V
1
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IDT82V2054 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD E1 SHORT HAUL LINE INTERFACE UNIT
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