參數(shù)資料
型號: IDT82V2052EPF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 49/70頁
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標準包裝: 45
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 82V2052EPF
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT
53
December 12, 2005
6.1
JTAG INSTRUCTIONS AND INSTRUCTION REG-
ISTER
The IR (Instruction Register) with instruction decode block is used to
select the test to be executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See Table-
42 for details of the codes and the instructions related.
6.2
JTAG DATA REGISTER
6.2.1
DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the producer number, part number and the
device revision, which can be used to verify the proper version or revision
number that has been used in the system under test. The IDR is 32 bits long
and is partitioned as in Table-43. Data from the IDR is shifted out to TDO
LSB first.
6.2.2
BYPASS REGISTER (BR)
The BR consists of a single bit. It can provide a serial path between the
TDI input and TDO output, bypassing the BSR to reduce test access times.
6.2.3
BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized and
read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is
related to one or more bits in the BSR. For details, please refer to the BSDL
file.
6.2.4
TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure-20
shows its state diagram following the description of each state. Note that
the figure contains two main branches to access either the data or instruc-
tion registers. The value shown next to each state transition in this figure
states the value present at TMS at each rising edge of TCK. Please refer
to Table-44 for details of the state description.
Table-42 Instruction Register Description
IR CODE
INSTRUCTION
COMMENTS
000
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST
instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by load-
ing the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary
scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
100
Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between
IDT82V2052E logic and the I/O pins is maintained. Primary device inputs
and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then
be viewed by shifting the boundary scan register using the Shift-DR state.
110
Idcode
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification
code can then be shifted out using the Shift-DR state.
111
Bypass
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to
bypass the device.
Table-43 Device Identification Register Description
Bit No.
Comments
0
Set to ‘1’
1-11
Producer Number
12-27
Part Number
28-31
Device Revision
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