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參數(shù)資料
| 型號： | IDT82V2052EPFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 2CH SHORT HAUL 80-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2052EPFG |
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
20
December 12, 2005
3.2.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75
or 120
internalimpedanceofTTIPn/TRINGn.IfT_TERM[2]issetto‘1’,theinternal
impedance matching circuit will be disabled. In this case, the external
impedancematchingcircuitwillbeusedtorealizetheimpedancematching.
Figure-6 shows the appropriate external components to connect with
the cable for one channel. Table-4 is the list of the recommended imped-
ance matching for transmitter.
In hardware control mode, TERMn pin can be used to select impedance
matchingforbothreceiverandtransmitteronaperchannelbasis.IfTERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used. When internal impedance net-
workisused,PULSnpinsshouldbesettoselectthespecificinternalimped-
ance in the corresponding channel. Refer to 5 HARDWARE CONTROL PIN
for details.
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-
for details.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
Loss of MCLK;
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
Note: The precision of the resistors should be better than ± 1%
3.2.5
TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-
for details.
3.3
RECEIVE PATH
The receive path consists of Receive Internal Termination, Monitor
Gain,Amplitude/WaveShapeDetector,DigitalTuningController,Adaptive
Equalizer, DataSlicer,CDR(Clock &Data Recovery),OptionalJitter Atten-
uator, Decoder and LOS/AIS Detector. Refer to Figure-5.
3.3.1
RECEIVE INTERNAL TERMINATION
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75
or
120
internalimpedanceofRTIPn/RRINGn.IfR_TERM[2]issetto‘1’,the
internal impedance matching circuit will be disabled. In this case, the exter-
nal impedance matching circuit will be used to realize the impedance
matching.
Figure-6 shows the appropriate external components to connect with
the cable for one channel. Table-5 is the list of the recommended imped-
ance matching for receiver.
Table-4 Impedance Matching for Transmitter
Cable
Internal Termination
External Termination
Configuration
T_TERM[2:0]
PULS[3:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
E1 / 75
000
0000
0
1XX
0001
9.4
E1 / 120
001
0001
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