參數(shù)資料
型號: IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/88頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標準包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應商設備封裝: 81-CABGA(8x8)
包裝: 托盤
2009 Integrated Device Technology, Inc.
DSC-6229/7
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
May 4, 2009
DUAL CHANNEL T1/E1/J1 LONG
HAUL/SHORT HAUL LINE INTER-
FACE UNIT
IDT82V2082
FEATURES:
Dual channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
Software programmable or hardware selectable on:
- Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild
Out)
- Line terminating impedance (T1:100
, J1:110 , E1: 75 /120 )
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS(QuasiRandomSequenceSignals)generationanddetection
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) and AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces and hardware control mode
Pin compatible to 82V2042E T1/E1/J1 Short Haul LIU and
82V2052E E1 Short Haul LIU
Available in 80-pin TQFP and 81-pin FPBGA
Green package options available
.
DESCRIPTION:
The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line
Interface Unit. In receive path, an Adaptive Equalizer is integrated to
removethedistortionintroducedbythecableattenuation.TheIDT82V2082
also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and
detects and reports the LOS conditions. In transmit path, there is an AMI/
B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter
Attenuator, which can be placed in either the receive path or the transmit
path. The Jitter Attenuator can also be disabled. The IDT82V2082 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
the chip, and different types of loopbacks can be set according to the appli-
cations. Four different kinds of line terminating impedance, 75
,100 ,
110
and 120 are selectable on a per channel basis. The chip also pro-
vides driver short-circuit protection and internal protection diode and sup-
ports JTAG boundary scanning. The chip can be controlled by either
software or hardware.
The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
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