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| 型號： | IDT82V2081PPG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 1CH 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2081PPG8 |
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15
INDUSTRIAL
TEMPERATURE RANGES
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3
FUNCTIONAL DESCRIPTION
3.1
CONTROL MODE SELECTION
The IDT82V2081 can be configured by software or by hardware. The
software control mode supports Serial Control Interface, Motorola Multi-
plexed Control Interface and Intel Multiplexed Control Interface. The Con-
trol mode is selected by MODE1 and MODE0 pins as follows:
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel Multiplexed microcontroller Interface consists of CS,
AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins.
Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0],
PATT[1:0], JA[1:0], MONT, TERM, EQ, RPD, MODE[1:0] and
RXTXM[1:0]. Refer to 5 HARDWARE CONTROL PIN SUMMARY
for details about hardware control.
3.2
T1/E1/J1 MODE SELECTION
When the chip is configured by software, T1/E1/J1 mode is selected by
the T1E1 bit (GCF, 02H). In E1 application, the T1E1 bit (GCF, 02H) should
be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
When the chip is configured by hardware, T1/E1/J1 mode is selected
by PULS[3:0] pins. These pins also determine transmit pulse template and
internal termination impedance. Refer to 5 HARDWARE CONTROL PIN
SUMMARY for details.
3.3
TRANSMIT PATH
The transmit path of IDT82V2081 consists of an Encoder, an optional
Jitter Attenuator, a Waveform Shaper, a set of LBOs, a Line Driver and a
Programmable Transmit Termination.
3.3.1
TRANSMIT PATH SYSTEM INTERFACE
The transmit path system interface consists of TCLK pin, TD/TDP pin
andTDN pin. InE1mode, TCLKis a2.048 MHzclock.In T1/J1mode, TCLK
is a 1.544 MHz clock. If TCLK is missing for more than 70 MCLK cycles, an
interrupt will be generated if it is not masked.
Transmit data is sampled on the TD/TDP and TDN pins by the active
edge of TCLK. The active edge of TCLK can be selected by the TCLK_SEL
bit (TCF0, 05H). And the active level of the data on TD/TDP and TDN can
be selected by the TD_INV bit (TCF0, 05H). In hardware control mode, the
falling edge of TCLK and the active high of transmit data are always used.
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TD pin is used
for transmitting data and the T_MD[1] bit (TCF0, 05H) should be set to ‘0’.
In Dual Rail Mode, both TDP pin and TDN pin are used for transmitting data,
the T_MD[1] bit (TCF0, 05H) should be set to ‘1’.
3.3.2
ENCODER
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 05H).
InSingleRailmode,whenE1modeisselected,theEncodercanbecon-
figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 05H).
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on
the TDP pin and a logic ‘0’ on the TDN pin results in a negative pulse on the
TTIP/TRING; a logic ‘0’ on TDP pin and a logic ‘1’ on TDN pin results in a
positive pulse on the TTIP/TRING. If both TDP and TDN are high or low,
the TTIP/TRING outputs a space (Refer to TD/TDP, TDN Pin Description).
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.3.3
PULSE SHAPER
The IDT82V2081 provides three ways of manipulating the pulse shape
before sending it. The first is to use preset pulse templates for short haul
application, the second is to use LBO (Line Build Out) for long haul appli-
cation and the other way is to use user-programmable arbitrary waveform
template.
In software control mode, the pulse shape can be selected by setting
the related registers.
In hardware control mode, the pulse shape can be selected by setting
PULS[3:0] pins. Refer to 5 HARDWARE CONTROL PIN SUMMARY for
details.
3.3.3.1 Preset Pulse Templates
For E1 applications, the pulse shape is shown in Figure-3 according to
the G.703 and the measuring diagram is shown in Figure-4. In internal
impedance matching mode, if the cable impedance is 75
, the PULS[3:0]
bits (TCF1, 06H) should be set to ‘0000’; if the cable impedance is 120
,
the PULS[3:0] bits (TCF1, 06H) should be set to ‘0001’. In external imped-
ance matching mode, for both E1/75
and E1/120 cable impedance,
PULS[3:0] should be set to ‘0001’.
Figure-3 E1 Waveform Template Diagram
Control Interface mode
00
Hardware interface
01
Serial Microcontroller Interface.
10
Parallel –Multiplexed -Motorola Interface
11
Parallel –Multiplexed -Intel Interface
-0 .6
-0 .4
-0 .2
0
0 .2
0 .4
0.6
-0 .2 0
0.00
0.20
0.40
0.60
0.8 0
1.0 0
1.20
T im e in U n it In te rva ls
N
or
m
alized
Am
plit
ude
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2082 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082_09 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082BFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082BFG | 功能描述:IC LIU T1/E1/J1 2CH 81BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA |
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