參數(shù)資料
型號(hào)： IDT82V3255TFG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： GREEN, TQFP-64
文件頁數(shù)： 18/127頁
文件大?。?/td> 868K
代理商： IDT82V3255TFG
IDT82V3255
WAN PLL
Functional Description
18
June 19, 2006
3.3
INPUT CLOCKS & FRAME SYNC SIGNALS
Altogether 5 clocks and 3 frame sync signals are input to the device.
3.3.1
INPUT CLOCKS
The device provides 5 input clock ports.
According to the input port technology, the input ports support the fol-
lowing technologies:
PECL/LVDS
CMOS
According to the input clock source, the following clock sources are
supported:
T1: Recovered clock from STM-N or OC-n
T2: PDH network synchronization timing
T3: External synchronization reference timing
IN1_CMOS ~ IN3_CMOS support CMOS input signal only and the
clock sources can be from T1, T2 or T3.
IN1_DIFF and IN2_DIFF support PECL/LVDS input signal only and
automatically detect whether the signal is PECL or LVDS. The clock
sources can be from T1, T2 or T3.
For SDH and SONET networks, the default frequency is different.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/
SDH
pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/
SDH
pin takes no effect.
3.3.2
FRAME SYNC INPUT SIGNALS
Three 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the
EX_SYNC1 to EX_SYNC3 pins respectively. They are CMOS inputs.
The input frequency should match the setting in the SYNC_FREQ[1:0]
bits.
Only one of the three frame sync input signals is used for frame sync
output signal synchronization. Refer to
Chapter 3.13.2 Frame SYNC
Output Signals
for details.
Table 3: Related Bit / Register in Chapter 3.3
Bit
Register
Address (Hex)
IN_SONET_SDH
SYNC_FREQ[1:0]
INPUT_MODE_CNFG
09
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