參數(shù)資料
型號: IDT82V3255TFG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: GREEN, TQFP-64
文件頁數(shù): 23/127頁
文件大?。?/td> 868K
代理商: IDT82V3255TFG
IDT82V3255
WAN PLL
Functional Description
23
June 19, 2006
3.6.2
FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to
Chapter 3.5 Input Clock Quality Moni-
toring
) do not affect the input clock selection.
3.6.3
AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to
Chapter 3.5 Input Clock Quality Monitoring
).
In all the qualified input clocks, the one with the highest priority is
selected. The priority is configured by the corresponding
INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the
INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one quali-
fied input clock is available and has the same priority, the input clock
with the smallest ‘n’ is selected. See
Table 9
for the ‘n’ assigned to the
input clock
.
Table 9: ‘n’ Assigned to the Input Clock
Input Clock
‘n’ Assigned to the Input Clock
IN1_CMOS
IN1_DIFF
IN2_CMOS
IN2_DIFF
IN3_CMOS
1
2
3
4
5
Table 10: Related Bit / Register in Chapter 3.6
Bit
Register
Address (Hex)
EXT_SW
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
0B
50
T0_INPUT_SEL[3:0]
T4_LOCK_T0
T0_FOR_T4
T4_INPUT_SEL[3:0]
T4_INPUT_SEL_CNFG
51
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
IN1_IN2_CMOS_SEL_PRIORITY_CNFG,
IN3_CMOS_SEL_PRIORITY_CNFG
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
T4_T0_REG_SEL_CNFG
27 *, 2A *
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
T4_T0_SEL
Note: *
The setting in the 27, 28 and 2A registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
28 *
07
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