參數(shù)資料
型號： IDT82V3280DQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： GREEN, TQFP-100
文件頁數(shù)： 42/167頁
文件大小： 1039K
代理商： IDT82V3280DQG
IDT82V3280
WAN PLL
Functional Description
42
June 19, 2006
3.13.2
FRAME SYNC OUTPUT SIGNALS
An 8 kHz and a 2 kHz frame sync signals are output on the
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
The two frame sync signals are derived from the T0 APLL output and
are aligned with the output clock. They can be synchronized to the frame
sync input signal.
If the frame sync input signal with respect to the T0 selected input
clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an external
sync alarm will be raised and EX_SYNC1 is disabled to synchronize the
frame sync output signals. The external sync alarm is cleared once
EX_SYNC1 with respect to the T0 selected input clock is within the limit.
If it is within the limit, whether EX_SYNC1 is enabled to synchronize the
frame sync output signal is determined by the AUTO_EXT_SYNC_EN
bit and the EXT_SYNC_EN bit. Refer to
Table 27
for details.
When the frame sync input signal is enabled to synchronize the
frame sync output signal, it should be adjusted to align itself with the T0
selected input clock. Nominally, the falling edge of EX_SYNC1 is aligned
with the rising edge of the T0 selected input clock. EX_SYNC1 may be
0.5 UI early/late or 1 UI late due to the circuit and board wiring delays.
Setting the sampling of EX_SYNC1 by the SYNC_PH1[1:0] bits will
compensate this early/late. Refer to
Figure 9
to
Figure 12
.
The EX_SYNC_ALARM_MON bit indicates whether EX_SYNC1 is in
external sync alarm status. The external sync alarm is indicated by the
EX_SYNC_ALARM
1
bit. If the EX_SYNC_ALARM
2
bit is ‘1’, the occur-
rence of the external sync alarm will trigger an interrupt.
The 8 kHz and the 2 kHz frame sync output signals can be inverted
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT3; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
Figure 9. On Target Frame Sync Input Signal Timing
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing
Table 27: Synchronization Control
AUTO_EXT_SYNC_EN EXT_SYNC_EN
Synchronization
don’t-care
0
1
0
1
1
Disabled
Enabled
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
T0 selected
input clock
Output clocks
EX_SYNC1
Frame sync
output signals
T0 selected
input clock
Output clocks
EX_SYNC1
Frame sync
output signals
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