參數(shù)資料
型號(hào): IDT82V3280DQG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: GREEN, TQFP-100
文件頁數(shù): 79/167頁
文件大?。?/td> 1039K
代理商: IDT82V3280DQG
IDT82V3280
WAN PLL
Programming Information
79
June 19, 2006
7.2.3
INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS
IN1_CNFG - Input Clock 1 Configuration
IN2_CNFG - Input Clock 2 Configuration
Address: 14H
Type: Read / Write
Default Value: X0000000
Bit
Name
Description
7
-
Reserved.
This bit should be set to match the clock input on IN1:
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
These bits select one of the four groups of leaky bucket configuration registers for IN1:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN1:
0000: 8 kHz. (default)
0001 ~ 1111: Reserved.
6
400HZ_SEL
5 - 4
BUCKET_SEL[1:0]
3 - 0
IN_FREQ[3:0]
Address: 15H
Type: Read / Write
Default Value: X0000000
Bit
Name
Description
7
-
Reserved.
This bit should be set to match the clock input on IN2:
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
These bits select one of the four groups of leaky bucket configuration registers for IN2:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2:
0000: 8 kHz. (default)
0001 ~ 1111: Reserved.
6
400HZ_SEL
5 - 4
BUCKET_SEL[1:0]
3 - 0
IN_FREQ[3:0]
7
6
5
4
3
2
1
0
-
400HZ_SEL
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
7
6
5
4
3
2
1
0
-
400HZ_SEL
BUCKET_SEL1
BUCKET_SEL0
IN_FREQ3
IN_FREQ2
IN_FREQ1
IN_FREQ0
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