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參數(shù)資料
| 型號： | IDT82V3280PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | GREEN, TQFP-100 |
| 文件頁數(shù)： | 3/167頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | IDT82V3280PFG |
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Table of Contents
3
June 19, 2006
FEATURES.............................................................................................................................................................................. 9
HIGHLIGHTS....................................................................................................................................................................................................9
MAIN FEATURES............................................................................................................................................................................................9
OTHER FEATURES.........................................................................................................................................................................................9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 11
1 PIN ASSIGNMENT ...........................................................................................................................................................12
2 PIN DESCRIPTION ..........................................................................................................................................................13
3 FUNCTIONAL DESCRIPTION .........................................................................................................................................19
3.1
RESET ...........................................................................................................................................................................................................19
3.2
MASTER CLOCK ..........................................................................................................................................................................................19
3.3
INPUT CLOCKS & FRAME SYNC SIGNAL .................................................................................................................................................20
3.3.1
Input Clocks .................................................................................................................................................................................... 20
3.3.2
Frame SYNC Input Signals ............................................................................................................................................................ 20
3.4
INPUT CLOCK PRE-DIVIDER ......................................................................................................................................................................21
3.5
INPUT CLOCK QUALITY MONITORING .....................................................................................................................................................23
3.5.1
LOS Monitoring .............................................................................................................................................................................. 23
3.5.2
Activity Monitoring ......................................................................................................................................................................... 23
3.5.3
Frequency Monitoring ................................................................................................................................................................... 24
3.6
T0 / T4 DPLL INPUT CLOCK SELECTION ..................................................................................................................................................25
3.6.1
External Fast Selection (T0 only) .................................................................................................................................................. 25
3.6.2
Forced Selection ............................................................................................................................................................................ 26
3.6.3
Automatic Selection ....................................................................................................................................................................... 26
3.7
SELECTED INPUT CLOCK MONITORING ..................................................................................................................................................27
3.7.1
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27
3.7.1.1
Fast Loss .......................................................................................................................................................................... 27
3.7.1.2
Coarse Phase Loss .......................................................................................................................................................... 27
3.7.1.3
Fine Phase Loss ............................................................................................................................................................... 27
3.7.1.4
Hard Limit Exceeding ....................................................................................................................................................... 27
3.7.2
Locking Status ............................................................................................................................................................................... 27
3.7.3
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28
3.8
SELECTED INPUT CLOCK SWITCH ...........................................................................................................................................................29
3.8.1
Input Clock Validity ........................................................................................................................................................................ 29
3.8.2
Selected Input Clock Switch ......................................................................................................................................................... 29
3.8.2.1
Revertive Switch ............................................................................................................................................................... 29
3.8.2.2
Non-Revertive Switch (T0 only) ........................................................................................................................................ 30
3.8.3
Selected / Qualified Input Clocks Indication ................................................................................................................................ 30
3.9
SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE .......................................................................................................31
3.9.1
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31
3.9.2
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33
3.10 T0 / T4 DPLL OPERATING MODE ...............................................................................................................................................................34
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34
3.10.1.3 Locked Mode .................................................................................................................................................................... 34
Table of Contents
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|---|---|
| IDT82V3288 | WAN PLL |
| IDT82V3288BC | WAN PLL |
| IDT82V3288BCG | WAN PLL |
| IDT85304-01 | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3280PFG8 | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280PFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3285 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3285AEQG | 功能描述:IC PLL WAN SE STRATUM 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3285AEQG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP |
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