參數(shù)資料
型號: IDT82V3280PFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 39/171頁
文件大小: 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: 82V3280PFG
IDT82V3280
WAN PLL
Programming Information
133
December 9, 2008
CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
Address: 64H
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 0
CURRENT_DPLL_FREQ[23:16]
The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mul-
tiplied by 0.000011, the current frequency offset of the T0/T4 DPLL output in ppm with respect to the master clock
will be gotten.
Address: 65H
Type: Read / Write
Default Value: 10001100
Bit
Name
Description
7
FREQ_LIMT_PH_LOS
This bit determines whether the T0/T4 DPLL in hard alarm status will result in it unlocked.
0: Disabled.
1: Enabled. (default)
6 - 0
DPLL_FREQ_SOFT_LIMT[6:0]
These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 and T4 paths in
ppm will be gotten.
The DPLL soft limit is symmetrical about zero.
Address: 66H
Type: Read / Write
Default Value: 10101011
Bit
Name
Description
7 - 0
DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
7
6543210
CURRENT_DP
LL_FREQ23
CURRENT_DP
LL_FREQ22
CURRENT_DP
LL_FREQ21
CURRENT_DP
LL_FREQ20
CURRENT_DP
LL_FREQ19
CURRENT_DP
LL_FREQ18
CURRENT_DP
LL_FREQ17
CURRENT_DP
LL_FREQ16
765
4
3
2
1
0
FREQ_LIMT_P
H_LOS
DPLL_FREQ_S
OFT_LIMT6
DPLL_FREQ_S
OFT_LIMT5
DPLL_FREQ_S
OFT_LIMT4
DPLL_FREQ_S
OFT_LIMT3
DPLL_FREQ_S
OFT_LIMT2
DPLL_FREQ_S
OFT_LIMT1
DPLL_FREQ_S
OFT_LIMT0
765
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT7
DPLL_FREQ_H
ARD_LIMT6
DPLL_FREQ_H
ARD_LIMT5
DPLL_FREQ_H
ARD_LIMT4
DPLL_FREQ_H
ARD_LIMT3
DPLL_FREQ_H
ARD_LIMT2
DPLL_FREQ_H
ARD_LIMT1
DPLL_FREQ_H
ARD_LIMT0
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