參數(shù)資料
型號: IDT89HPES16NT2ZBBC
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/29頁
文件大小: 0K
描述: IC PCI SW 16LANE 2PORT 484-CABGA
標(biāo)準(zhǔn)包裝: 60
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費(fèi)品
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-CABGA(23x23)
包裝: 托盤
其它名稱: 89HPES16NT2ZBBC
1 of 29
January 5, 2009
2009 Integrated Device Technology, Inc.
DSC 6925
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The 89HPES16NT2 is a member of the IDT PRECISE family of
PCI Express switching solutions offering the next-generation I/O inter-
connect standard. The PES16NT2 is a 16-lane, 2-port peripheral chip
that provides high-performance switching and non-transparent bridging
(NTB) functions between a PCIe upstream port and an NTB down-
stream port. The PES16NT2 is a part of the IDT PCIe System Intercon-
nect Products and is intended to be used with IDT PCIe System
Interconnect Switches. Together, the chipset targets multi-host and intel-
ligent I/O applications such as communications, storage, and blade
servers where inter-domain communication is required.
Features
High Performance PCI Express Switch
Sixteen PCI Express lanes (2.5Gbps), two switch ports
Delivers 64 Gbps (8 GBps) of aggregate switching capacity
Low latency cut-through switch architecture
Support for Max Payload size up to 2048 bytes
Supports one virtual channel and eight traffic classes
PCI Express Base specification Revision 1.0a compliant
Flexible Architecture with Numerous Configuration Options
Supports automatic per port link width negotiation (x8, x4, x2,
or x1)
Static lane reversal on all ports
Automatic polarity inversion on all lanes
Supports locked transactions, allowing use with legacy soft-
ware
Ability to load device configuration from serial EEPROM
Ability to control device via SMBus
Non-Transparent Port
Crosslink support on NTB port
Four mapping windows supported
Each may be configured as a 32-bit memory or I/O window
May be paired to form a 64-bit memory window
Interprocessor communication
Thirty-two inbound and outbound doorbells
Four inbound and outbound message registers
Two shared scratchpad registers
Allows up to sixteen masters to communicate through the non-
transparent port
No limit on the number of supported outstanding transactions
through the non-transparent bridge
Completely symmetric non-transparent bridge operation
allows similar/same configuration software to be run
Supports direct connection to a transparent or non-transparent
port of another switch
Highly Integrated Solution
Requires no external components
Incorporates on-chip internal memory for packet buffering and
queueing
Integrates sixteen 2.5 Gbps embedded full duplex SerDes, 8B/
10B encoder/decoder (no separate transceivers needed)
Block Diagram
Figure 1 Internal Block Diagram
16 PCI Express Lanes
x8 Upstream Port and One x8 Downstream Port
2-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
...
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Non-
Transparent
Bridge
89HPES16NT2
Data Sheet
16-Lane 2-Port Non-Transparent
PCI Express Switch
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