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參數(shù)資料
型號: IDT89HPES16NT2ZBBC
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/29頁
文件大?。?/td> 0K
描述: IC PCI SW 16LANE 2PORT 484-CABGA
標(biāo)準(zhǔn)包裝: 60
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費品
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-CABGA(23x23)
包裝: 托盤
其它名稱: 89HPES16NT2ZBBC
2 of 29
January 5, 2009
IDT 89HPES16NT2 Data Sheet
Reliability, Availability, and Serviceability (RAS) Features
Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Supports ECRC pass-through
Supports Hot-Swap
Power Management
Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
Unused SerDes are disabled
Testability and Debug Features
Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
Ability to read and write any internal register via the SMBus
Ability to bypass link training and force any link into any mode
Provides statistics and performance counters
Two SMBus Interfaces
Slave interface provides full access to all software-visible
registers by an external SMBus master
Master interface provides connection for an optional serial
EEPROM used for initialization
Master and slave interfaces may be tied together so the switch
can act as both master and slave
Eight General Purpose Input/Output pins
Packaged in a 23mm x 23mm 484-ball BCG with 1mm ball
spacing
Product Description
Utilizing standard PCI Express interconnect, the PES16NT2 provides
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-trans-
parent bridging, the PES16NT2 is part of the IDT PCIe System Intercon-
nect Products that target multi-host and intelligent I/O applications
requiring inter-domain communication. The PES16NT2 provides 64
Gbps (8 GBps) of aggregated, full-duplex switching capacity through 16
integrated serial lanes, using proven and robust IDT technology. Each
lane provides 2.5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 1.0a.
The PES16NT2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link,
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 1.0a. The PES16NT2 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management.
Switch Configuration
The PES16NT2 is a two port switch that contains sixteen PCI
Express lanes. Each of the two ports is statically allocated eight lanes
with ports labeled as A and C. Port A is the upstream port and port C is
the non-transparent downstream port.
During link training, link width is automatically negotiated. Each
PES16NT2 port is capable of independently negotiating to a x8, x4, x2,
or x1 width. Thus, the PES16NT2 may be used in virtually any two port
switch configuration (e.g., {x8, x8}, {x4, x4}, {x4, x2}, etc.). The
PES16NT2 supports static lane reversal. For example, lane reversal for
upstream port A may be configured by asserting the PCI Express Port A
Lane Reverse (PEALREV) input signal or through serial EEPROM or
SMBus initialization. Lane reversal for port C may be enabled via a
configuration space register, serial EEPROM, or the SMBus.
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