參數(shù)資料
型號(hào)： IDT89HPES24NT3ZBBX
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 26/31頁(yè)
文件大小： 0K
描述： IC PCI SW 24LANE 3PORT 420-SBGA
標(biāo)準(zhǔn)包裝： 40
系列： PRECISE™
類型： PCI Express 開(kāi)關(guān) - Gen1
應(yīng)用： 服務(wù)器，儲(chǔ)存，通信，嵌入式，消費(fèi)品
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA
供應(yīng)商設(shè)備封裝： 420-SBGA（27x27）
包裝： 托盤
其它名稱： 89HPES24NT3ZBBX
4 of 31
January 5, 2009
IDT 89HPES24NT3 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24NT3. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PEALREV
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[7:0]
PEARN[7:0]
I
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[7:0]
PEATN[7:0]
O
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PEBLREV
I
PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PEBRP[7:0]
PEBRN[7:0]
I
PCI Express Port B Serial Data Receive. Differential PCI Express receive
pairs for port B.
PEBTP[7:0]
PEBTN[7:0]
O
PCI Express Port B Serial Data Transmit. Differential PCI Express trans-
mit pairs for port B
PECLREV
I
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[7:0]
PECRN[7:0]
I
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[7:0]
PECTN[7:0]
O
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM is being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins (Part 1 of 2)
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