參數(shù)資料
型號: IDT89HPES24NT3ZBBXG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 29/31頁
文件大小: 0K
描述: IC PCI SW 24LANE 3PORT 420-SBGA
標(biāo)準(zhǔn)包裝: 40
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費(fèi)品
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA
供應(yīng)商設(shè)備封裝: 420-SBGA(27x27)
包裝: 托盤
其它名稱: 89HPES24NT3ZBBXG
7 of 31
January 5, 2009
IDT 89HPES24NT3 Data Sheet
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 6 Power and Ground Pins
Signal
Type
Name/Description
Table 5 Test Pins (Part 2 of 2)
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