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March 27, 2008
2008 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Device Overview
The 89HPES8T5 is a member of the IDT PRECISE family of PCI
Express switching solutions. The PES8T5 is an 8-lane, 5-port peripheral
chip that performs PCI Express packet switching with a feature set opti-
mized for high performance applications such as servers, storage and
communications/networking. It provides connectivity and switching func-
tions between a PCI Express upstream port and up to four downstream
ports and supports switching between downstream ports.
Features
◆
High Performance PCI Express Switch
– Eight 2.5 Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
Supports device power management states: D0, D3hot and
D3cold
– Unused SerDes are disabled
Block Diagram
Figure 1 Internal Block Diagram
5-Port Switch Core / 8 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 0)
(Port 2)
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
SerDes
Phy
Logical
Layer
Mux / Demux
Transaction Layer
Data Link Layer
(Port 3)
(Port 5)
SerDes
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Mux / Demux
(Port 4)
SerDes
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Mux / Demux
89HPES8T5
Data Sheet
8-Lane 5-Port
PCI Express Switch