參數(shù)資料
型號(hào): IDTCSPT857CBVG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56
封裝: VFBGA-56
文件頁數(shù): 12/15頁
文件大小: 138K
代理商: IDTCSPT857CBVG8
6
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. AVDD nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD nominal is 2.6V for PC3200.
3. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
FUNCTION TABLE(1)
INPUTS
OUTPUTS
AVDD
PWRDWN
CLK
Y
FBOUT
PLL
GND
H
L
H
L
H
L
H
Bypassed/OFF
GND
H
L
H
L
H
L
Bypassed/OFF
X
L
H
Z
OFF
X
L
H
L
Z
OFF
Nominal(2)
HL
H
L
HL
H
ON
Nominal(2)
HH
L
H
L
H
L
ON
Nominal(2,3)
X
<20MHz
Z
OFF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 -
PC2700
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIK
InputClampVoltage(AllInputs)
VDDQ = 2.3V, II = -18mA
– 1.2
V
VIL(dc)
StaticInputLOWVoltage
PWRDWN
– 0.3
0.7
V
VIH(dc)
Static Input HIGH Voltage
PWRDWN
1.7
VDDQ + 0.3
VIL(ac)
DynamicInputLOWVoltage
CLK, CLK, FBIN, FBIN
0.7
V
VIH(ac)
Dynamic Input HIGH Voltage
CLK, CLK, FBIN, FBIN
1.7
VDDQ
VOL
OutputLOWVoltage
AVDD/VDDQ = Min., IOL = 100
A
0.1
V
AVDD/VDDQ = Min., IOL = 12mA
0.6
VOH
Output HIGH Voltage
AVDD/VDDQ = Min., IOH = -100
AVDDQ – 0.1
V
AVDD/VDDQ = Min., IOH = -12mA
1.7
VIX
InputDifferentialCrossVoltage
VDDQ/2 – 0.2
VDDQ/2 + 0.2
V
VID(DC)(1)
DCInputDifferentialVoltage
0.36
VDDQ + 0.6
V
VID(AC)(1)
ACInputDifferentialVoltage
0.7
VDDQ + 0.6
V
IIN
InputCurrent
VDDQ = 2.7V, VI = 0V to 2.7V
±10
A
IDDPD
Power-Down Current on VDDQ and AVDD
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
100
200
A
IDDQ
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 200MHz, 120
/14pF
320
360
mA
AVDD/VDDQ = Max., CLK = 170MHz, 120
/14pF
250
300
IADD
Dynamic Power Supply Current on AVDD
AVDD/VDDQ = Max., CLK = 170MHz
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
相關(guān)PDF資料
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IDTCSPT857CNL8 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
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