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參數資料
| 型號： | IDTCSPT857CBVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| 封裝： | VFBGA-56 |
| 文件頁數： | 13/15頁 |
| 文件大?。?/td> | 138K |
| 代理商： | IDTCSPT857CBVG8 |
7
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIK
InputClampVoltage(AllInputs)
VDDQ = 2.5V, II = -18mA
– 1.2
V
VIL(dc)
StaticInputLOWVoltage
PWRDWN
– 0.3
0.7
V
VIH(dc)
Static Input HIGH Voltage
PWRDWN
1.7
VDDQ + 0.3
VIL(ac)
DynamicInputLOWVoltage
CLK, CLK, FBIN, FBIN
0.7
V
VIH(ac)
Dynamic Input HIGH Voltage
CLK, CLK, FBIN, FBIN
1.7
VDDQ
VOL
OutputLOWVoltage
AVDD/VDDQ = Min., IOL = 100
A
0.1
V
AVDD/VDDQ = Min., IOL = 12mA
0.6
VOH
Output HIGH Voltage
AVDD/VDDQ = Min., IOH = -100
AVDDQ – 0.1
V
AVDD/VDDQ = Min., IOH = -12mA
1.7
VIX
InputDifferentialCrossVoltage
VDDQ/2 – 0.2
VDDQ/2 + 0.2
V
VID(DC)(1)
DCInputDifferentialVoltage
0.36
VDDQ + 0.6
V
VID(AC)(1)
ACInputDifferentialVoltage
0.7
VDDQ + 0.6
V
IIN
InputCurrent
VDDQ = 2.7V, VI = 0V to 2.7V
±10
A
IDDPD
Power-Down Current on VDDQ and AVDD
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L
100
200
A
IDDQ
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 200MHz, 120
/14pF
320
360
mA
AVDD/VDDQ = Max., CLK = 200MHz, 120
/14pF
250
300
IADD
Dynamic Power Supply Current on AVDD
AVDD/VDDQ = Max., CLK = 200MHz
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
TIMING REQUIREMENTS FOR PC3200
Symbol
Parameter
Min.
Max.
Unit
fCLK
OperatingClockFrequency(1,2)
60
220
MHz
ApplicationClockFrequency(1,3)
60
220
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
100
s
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
TIMING REQUIREMENTS FOR PC1600 - PC2700
Symbol
Parameter
Min.
Max.
Unit
fCLK
OperatingClockFrequency(1,2)
60
200
MHz
ApplicationClockFrequency(1,3)
60
200
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
100
s
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
相關PDF資料 |
PDF描述 |
|---|---|
| IDTCSPT857CNL8 | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| IDTCSPT857CPAI8 | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| IDTCSPT857CNLG8 | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| IDTCSPT857CBVG | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56 |
| IDTCSPT857CPA8 | 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDTCSPT857CBVI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLG | 功能描述:IC SDRAM CLK DVR 1:10 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLG8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| IDTCSPT857CNLGI | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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