參數(shù)資料
型號(hào): IDTCSPT857CNLG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
封裝: GREEN, VFQFPN-40
文件頁數(shù): 14/15頁
文件大小: 145K
代理商: IDTCSPT857CNLG8
8
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
SWITCHING CHARACTERISTICS FOR PC1600 - PC2700
Symbol
Description
Test Conditions
Min.
Typ.(1)
Max.
Unit
tPLH(1)
LOW to HIGH Level Propagation Delay Time
Test mode, CLK to any output
4.5
ns
tPHL(1)
HIGH to LOW Level Propagation Delay Time
Test mode, CLK to any output
4.5
ns
tJIT(PER)
Jitter (period), see figure 6
66MHz
– 90
90
ps
100/ 133/ 167/ 200 MHz
– 75
75
tJIT(CC)
Jitter (cycle-to-cycle), see figure 3
66MHz
– 180
180
ps
100/ 133/ 167/ 200 MHz
– 75
75
tJIT(HPER)
Half-Period Jitter, see figure 7
66MHz
– 160
160
ps
100/ 133/ 167/ 200 MHz
– 100
100
tSLR(O)
Output Clock Slew Rate (Single-Ended)
100/ 133/ 167/ 200 MHz (20% to 80%)
1
2.5
V/ns
tSLR(I)
Input Clock Slew Rate
1
4
V/ns
t(
)
Static Phase Offset, see figure 4(2,3)
66/ 100/ 133/ 167/ 200 MHz
– 50
50
ps
tSK(O)
Output Skew, see figure 5
75
ps
tR,tF
Output Rise and Fall Times (20% to 80%)
Load: 120
Ω / 14pF
650
900
ps
VOX(5)
OutputDifferentialVoltage
Differentialoutputsareterminated
VDDQ/2
V
with 120
Ω
– 0.15
+ 0.15
The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:
SSC
ModulationFrequency
30
50
KHz
SSC
Clock Input Frequency Deviation
0
-0.5
%
f3dB
PLL Loop Bandwidth
5
MHz
NOTES:
1.
Refers to transition of non-inverting output.
2.
Static phase offset does not include jitter.
3.
t(
φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4.
The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5.
VOX is specified at the SDRAM clock input or test load.
相關(guān)PDF資料
PDF描述
IDTCSPT857CBVG 857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA56
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