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參數(shù)資料
| 型號(hào)： | IDTCSPU877ABV8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | VFBGA-52 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 115K |
| 代理商： | IDTCSPU877ABV8 |
1
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
2006
Integrated Device Technology, Inc.
DSC-6495/8
c
IDTCSPU877A
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
OCTOBER 2006
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
Operating frequency: 125MHz to 340MHz
Very low skew:
≤≤≤≤≤40ps
Very low jitter:
≤≤≤≤≤40ps
1.8V AVDD and 1.8V VDDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.
DESCRIPTION:
TheCSPU877AisaPLLbasedclockdriverthatactsasazerodelaybuffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential
output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output
(FBOUT,FBOUT). Externalfeedbackpins(FBIN, FBIN)forsynchronization
oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDDcontrolthe
power-down and test mode logic. When AVDD is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan
500
μA.
TheCSPU877Arequiresnoexternalcomponentsandhasbeenoptimised
forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty
cycle over the operating voltage and temperature range. The CSPU877A,
designedforuseinbothmoduleassembliesandsystemmotherboardbased
solutions,providesanoptimumhigh-performanceclocksource.
The CSPU877A is available in Commercial Temperature Range (0°C to
+70°C). See Ordering Information for details.
APPLICATIONS:
Meets or exceeds JEDEC standard 82.8 for registered DDR2
clock driver
Along with SSTU32864/65/66, DDR2 register, provides complete
solution for DDR2 DIMMs
Y0
FBOUT
Y1
Y5
Y4
Y3
Y2
Y8
Y6
Y7
Y9
FBOUT
FBIN
PLL
CLK
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AVDD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
Ω -100KΩ
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| IDTCSPU877NL8 | CSPU877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| IDTCSPUA877BVG | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), BGA52 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPU877ABVG | 功能描述:IC SDRAM CLK DVR 1:10 52-VFBGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTCSPU877ABVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPU877ANL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ANLG | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPU877ANLG8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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