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參數(shù)資料
| 型號(hào)： | IDTCSPT857DPAGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DVR SDRAM 48-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，零延遲緩沖器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR，SDRAM |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 220MHz |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | CSPT857DPAGI8 |
7
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIK
Input Clamp Voltage (All Inputs)
VDDQ = 2.5V, II = -18mA
– 1.2
V
VIL(dc)
Static Input LOW Voltage
PWRDWN
– 0.3
0.7
V
VIH(dc)
Static Input HIGH Voltage
PWRDWN
1.7
VDDQ + 0.3
VIL(ac)
Dynamic Input LOW Voltage
CLK,
CLK, FBIN, FBIN
0.7
V
VIH(ac)
Dynamic Input HIGH Voltage
CLK,
CLK, FBIN, FBIN
1.7
VDDQ
VOL
Output LOW Voltage
AVDD/VDDQ = Min., IOL = 100
μA
0.1
V
AVDD/VDDQ = Min., IOL = 12mA
0.6
VOH
Output HIGH Voltage
AVDD/VDDQ = Min., IOH = -100
μAVDDQ – 0.1
V
AVDD/VDDQ = Min., IOH = -12mA
1.7
VIX
Input Differential Cross Voltage
VDDQ/2 – 0.2
VDDQ/2 + 0.2
V
VID(DC)(1)
DC Input Differential Voltage
0.36
VDDQ + 0.6
V
VID(AC)(1)
AC Input Differential Voltage
0.7
VDDQ + 0.6
V
IIN
InputCurrent
VDDQ = 2.7V, VI = 0V to 2.7V
±10
μA
IDDPD
Power-Down Current on VDDQ and AVDD
AVDD/VDDQ = Max., CLK = 0MHz or
PWRDWN = L
100
200
μA
IDDQ
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 200MHz, 120
Ω/14pF
320
360
mA
AVDD/VDDQ = Max., CLK = 200MHz, 120
Ω/14pF
250
300
IADD
Dynamic Power Supply Current on AVDD
AVDD/VDDQ = Max., CLK = 200MHz
12
mA
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on
CLK.
TIMING REQUIREMENTS FOR PC3200
Symbol
Parameter
Min.
Max.
Unit
fCLK
Operating Clock Frequency(1,2)
60
220
MHz
Application Clock Frequency(1,3)
60
220
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
100
μs
NOTES:
1.
The PLL will track a spread spectrum clock input.
2.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3.
Application clock frequency is the range over which timing specifications apply.
4.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
TIMING REQUIREMENTS FOR PC1600 - PC2700
Symbol
Parameter
Min.
Max.
Unit
fCLK
Operating Clock Frequency(1,2)
60
200
MHz
Application Clock Frequency(1,3)
60
200
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(4)
100
μs
NOTES:
1.
The PLL will track a spread spectrum clock input.
2.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3.
Application clock frequency is the range over which timing specifications apply.
4.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPT857DPAI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPFI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPN | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPNI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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