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參數(shù)資料
| 型號： | IDTCSPUA877ABVG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | GREEN, VFBGA-52 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 127K |
| 代理商： | IDTCSPUA877ABVG |
7
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1)
Symbol
Description
t
EN
OE to any Y/
Y
t
DIS
OE to any Y/
Y
s
LR(I)
Output Enable (
OE
)
Input Clock Slew Rate, measured single-ended
s
LR(O)(4)
Output Clock Slew Rate, measured single-ended 160 to 410
V
OX(6)
Output Differential-Pair Cross-Voltage
t
JIT(CC+)
Cycle-to-Cycle Period Jitter
t
JIT(CC-)
Cycle-to-Cycle Period Jitter
t
(
)(5)
Static Phase Offset
t
(
)DYN(7)
Dynamc Phase Offset
f
CK
(MHz)
160 to 410
160 to 410
160 to 410
160 to 410
Mn.
0.5
1
1.5
Typ.
(2)
2.5
2.5
Max.
8
8
4
3
Unit
ns
ns
V/ns
V/ns
V
ps
ps
ps
ps
160 to 410
160 to 410
160 to 410
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 270
271 to 410
271 to 410
271 to 410
(V
DDQ
/2) -0.1
0
0
-50
-50
t
(
)DYN(MIN)
-40
t
JIT(PER)MIN
-75
-50
(V
DDQ
/2) +0.1
40
-40
50
50
t
(
)DYN(MAX)
40
t
SK(O)MAX
40
t
JIT(PER)MAX
75
50
80
60
t
SK(O)(7)
Output Clock Skew
ps
t
JIT(PER)(3,7)
Period Jitter
ps
t
JIT(HPER)(3)
Half-Period Jitter
ps
Σ
t
(SU)(7)
Σ
t
(H)(7)
The PLL on the CSPUA877A will meet all the above test parameters while supporting SSC synthesizers with the following parameters:
SSC Modulation Frequency
SSC Clock Input Frequency Deviation
CSPUA877A PLL designs should target the value below to mnimze SSC-induced skew:
PLL Loop Bandwidth (-3dB fromunity gain)
|t
JIT(PER)
|+ |t
(
)DYN
|+ t
SK(O)
|t
(
)DYN
|+ t
SK(O)
ps
ps
30
0
33
0.5
KHz
%
2
MHz
NOTES:
1. There are two different termnations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage
only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50
Ω
equal length cables with SMA connectors
on the test board.
2. Refers to transition of non-inverting output.
3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other.
4. To elimnate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK,
CLK
) and feedback clock input (FBIN,
FBIN
) are recommended
to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nomnal values is not mandatory if it can be adequately demonstrated
that alternative characteristics meet the requirements of the registered DDR2 DIMMapplication.
5. Static phase offset does not include jitter.
6. V
OX
is specified at the DDR DRAMclock input or test load.
7. In the frequency range of 271 - 410MHz, the mn and max values for t
JIT
(
PER
) and
t
(
)DYN
, and the max value for t
SK
(
O
), must not exceed the corresponding mn and max values
of the 160 - 270MHz range. Also, the sumof the specified values for
|t
JIT(PER)
| |t
(
)DYN
| and t
SK(O)
must meet the requirement for
Σ
t
(SU),
and the sumof the specified values
for
|t
(
)DYN
|and t
SK(O)
must meet the requirement for
Σ
t
(H).
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