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參數(shù)資料
| 型號(hào)： | IDTCV110JP |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| 中文描述： | 可編程FLEXPC時(shí)鐘P4處理器 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | IDTCV110JP |
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COMMERCIAL TEMPERATURE RANGE
IDTCV110J
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
1
MAY 2004
IDTCV110J
COMME RCIAL T E MPE RAT URE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
XTAL
Osc Amp
SM Bus
Controller
Control
Logic
CPU CLK
Output Buffers
Stop Logic
X1
X2
SDATA
SCLK
V
TT_PWRGD
#/PD
FSA.B.C
I
REF
CPU[1:0]
REF
CPU_ITP/SRC7
PLL1
SSC
N Programmable
ITP_EN
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
I
REF
SRC[6:1]
48MHz
DOT96
PLL2
SSC
N Programmable
PLL3
PCI[5:0], PCIF[2:0]
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-6507/12
FEATURES:
One high precision PLL for CPU, SSC, and N programming
One high precision PLL for SRC/PCI/SATA, SSC, and N
programming
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Support spread spectrum modulation, down spread 0.5%
Support SMBus block read/write, index read/write
Selectable output strength for REF
Allows for CPU frequency to change to a higher frequency for
maximum system computing power
Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV110J is a 56 pin clock device. The CPU output buffer is designed to
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced I
REF
to reduce the impact of V
DD
variation on differential
outputs, which can provide more robust systemperformance.
Static PLL frequency divide error can be as low as 36 ppm worse case 114
ppm providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock
has its own Spread Spectrumselection, which allows for isolated changes
instead of affecting other clock groups.
OUTPUTS:
2*0.7V current –mode differential CPU CLK pair
6*0.7V current –mode differential SRC CLK pair, one dedicated
for SATA
One CPU_ITP/SRC selectable CLK pair
9*PCI, 3 free running, 33.3MHz
1*96MHz, 1*48MHz
1*REF
K EY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCV110JPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110LPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110LPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
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