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參數(shù)資料
| 型號： | IDTCSPUA877ANLG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | GREEN, PLASTIC, VFQFPN-40 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 127K |
| 代理商： | IDTCSPUA877ANLG |
6
COMMERCIAL TEMPERATURE RANGE
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C
Symbol
Parameter
V
IK
Input Clamp Voltage (All Inputs)
V
DDQ
= 1.7V, I
I
= -18mA
V
IL(2)
Input LOW Voltage (OE, OS, CLK,
CLK
)
V
IH(2)
Input HIGH Voltage (OE, OS, CLK,
CLK
)
V
IN(1)
Input Signal Voltage
V
ID(DC)(2)
DC Input Differential Voltage
V
OD(3)
Output Differential Voltage
A
VDD
/V
DDQ
= 1.7V
V
OH
Output HIGH Voltage
I
OH
= -100
μ
A, V
DDQ
= 1.7V to 1.9V
I
OH
= -9mA, V
DDQ
= 1.7V
V
OL
Output LOW Voltage
I
OL
= 100
μ
A, V
DDQ
= 1.7V to 1.9V
I
OL
= 9mA, V
DDQ
= 1.7V
I
ODL
Output Disabled LOW Current
OE = L, V
ODL
= 100mV, A
VDD
/V
DDQ
= 1.7V
I
IN
Input Current CLK,
CLK
A
VDD
/V
DDQ
= Max., V
I
= 0V to V
DDQ
OE, OS, FBIN,
FBIN
I
DDLD
Static Supply Current (I
DDQ
and I
ADD
)
A
VDD
/V
DDQ
= Max., CLK and
CLK
= GND
I
DD
Dynamc Power Supply Current
A
VDD
/V
DDQ
= Max., CLK = 410MHz
(I
DDQ
and I
ADD
)
(4,5)
Conditions
Mn.
0.65V
DDQ
-0.3
0.3
0.6
V
DDQ
- 0.2
1.1
Typ.
Max.
– 1.2
0.35V
DDQ
V
DDQ
+ 0.3
V
DDQ
+ 0.4
0.1
0.6
±250
±10
500
300
Unit
V
V
V
V
V
V
V
100
μ
A
μ
A
μ
A
mA
NOTES:
1. V
IN
specifies the allowable DC excursion of each different output.
2. V
ID
is the magnitude of the difference between the input level on CLK and the input level on
CLK
. The CLK and
CLK
V
IH
and V
IL
limts are used to define the DC LOW and HIGH
levels for the power down mode.
3. V
OD
is the magnitude of the difference between the true output level and the complementary level.
4. All Outputs are left open (unconnected to PCB).
5. Total I
DD
= I
DDQ
+ I
ADD
= F
CK
*C
PD
*V
DDQ
, for Cpd = (I
DDQ
+ I
ADD
) / (F
CK
*V
DDQ
) where F
CK
is the input frequency, V
DDQ
is the power supply, and C
PD
is the Power Dissipation Capacitance.
TIMING REQUIREMENTS
Symbol
Parameter
f
CLK
Operating Clock Frequency
(1,2,5)
Application Clock Frequency
(1,3,5)
t
DC
Input Clock Duty Cycle
t
L
Stabilization Time
(4)
Mn.
125
160
40
Max.
410
410
60
6
Unit
MHz
MHz
%
μ
s
NOTES:
1. The PLL will track a spread spectrumclock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timng specifications. To be used only for low speed systemdebug.
3. Application clock frequency is the range over which timng specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the
stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and
CLK
go to a logic LOW state, enters
the power-down mode, and later return to active operation. CLK and
CLK
may be left floating after they have been driven LOW for one complete clock cycle.
5. Will lock to input frequency as low as 30MHz at roomtemperature and nomnal or higher supply voltage (1.8V - 1.9V).
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