參數(shù)資料
型號: IDTCV115-2PVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/19頁
文件大小: 0K
描述: IC FLEXPC CLK PROGR P4 56-TSSOP
產(chǎn)品變化通告: Product Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 1,000
系列: FlexPC™
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU,SATA CPU
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: CV115-2PVG8
COMMERCIALTEMPERATURERANGE
IDTCV115-2
PROGRAMMABLEFLEXPC CLOCKFORP4PROCESSOR
1
APRIL 2004
IDTCV115-2
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
SATA PLL
SCC
SATA/
CPU[1:0]
SRC[6:5] [3:1]
USB48
DOT96
PCI[4:0], PCIF[2:0]
SRC4 - SATA
PCI/
PCIE/
Host/
48MHz/
96MHz/
MUX
PCIEX PLL
SCC
N Programming
CPU PLL
SCC
N Programming
Fixed PLL
No SCC
14.318MHz
Osc
CPU_ITP/
SRC7
RESET
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC 6544/9
FEATURES:
One high precision N Programming PLL for CPU
One high precision N Programming PLL for SRC/PCI
One high precision PLL for SATA
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Support multiple spread spectrum modulation, down and
center
Support SMBus block read/write, index read/write
Selectable output strength for REF, PCI, and 48MHz
Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV115-2 is a 56 pin clock device, complying the latest Intel CK410
requirements, for Intel advance P4 processors. The CPU output buffer is
designed to support up to 400MHz processor. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced IREF to reduce the impact of VDD variation on differential
outputs, which can provide more robust system performance.
Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection,
which allows for isolated changes instead of affecting other clock groups.
KEY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
OUTPUTTABLE
CPU
CPU_ITP/SRC
SRC
SATA
PCI/PCIF
REF/PCI
REF
DOT96
24_48MHz
RESET
TURBO
2
1
5181
1
2
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