參數(shù)資料
型號: IDTCV133PAG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/26頁
文件大?。?/td> 0K
描述: IC FLEXPC CLK PROGR P4 56-TSSOP
產(chǎn)品變化通告: Product Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 2,000
系列: FlexPC™
類型: PC 時鐘
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:17
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: CV133PAG8
COMMERCIALTEMPERATURERANGE
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
1
JANUARY 2005
IDTCV133
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
SM Bus
Controller
SEL
100/96MHz
Control
Logic
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
SDATA
SCLK
VTT_PWRGD#/PD
FSA.B.C
IREF
SRC[5:1]
48MHz
DOT96
PLL3
SSC
N Programmable
PLL4
PCI[3:0], PCIF[1:0]
XTAL
Osc Amp
CPU CLK
Output Buffer
Stop Logic
IREF
X1
X2
CPU[1:0]
REF
CPU_ITP/SRC7
PLL1
SSC
N Programmable
ITP_EN
PCI_STOP#
CPU_STOP#
LVDS
PLL2
SSC
CLKREQA#
CLKREQB#
SEL100/96#
LVDS CLK
Output Buffer
Stop Logic
IREF
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
DSC 6564/14
FEATURES:
Power management control suitable for notebook applications
One high precision PLL for CPU, SSC and N programming
One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Support spread spectrum modulation, –0.5 down spread and
others
Support SMBus block read/write, index read/write
Selectable output strength for REF
Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
Smooth transition for N programming
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV133 is a 56 pin clock device, incorporating both Intel CK410M and
CKSSCD requirements, for Intel advance P4 processors. The CPU output
buffer is designed to support up to 400MHz processor. This chip has four PLLs
inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device
alsoimplementsBand-gapreferencedIREFtoreducetheimpactofVDDvariation
on differential outputs, which can provide more robust system performance.
Each CPU/SRC/LVDS has its own Spread Spectrum selection.
OUTPUTS:
2*0.7V current –mode differential CPU CLK pair
5*0.7V current –mode differential SRC CLK pair
One CPU_ITP/SRC selectable CLK pair
6*PCI, 2 free running, 33.3MHz
1*96MHz, 1*48MHz
1*REF
One 100/96 MHz differential LVDS
KEY SPECIFICATION:
CPU CLK cycle to cycle jitter < 100ps
SRC CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 500ps
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