參數(shù)資料
型號(hào): IDTCV146PVG8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 0K
描述: IC FLEXPC CLK PROGR P4 56-SSOP
產(chǎn)品變化通告: Product Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝: 1,000
系列: FlexPC™
類型: PC 時(shí)鐘
PLL:
主要目的: Intel CPU,SATA CPU
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:18
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: CV146PVG8
COMMERCIALTEMPERATURERANGE
IDTCV146
PROGRAMMABLEFLEXPC CLOCKFORP4PROCESSOR
1
APRIL 2005
IDTCV146
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
XTAL
Osc Amp
SM Bus
Controller
Control
Logic
CPU CLK
Output Buffers
Stop Logic
XTAL_IN
XTAL_OUT
SDATA
SCLK
VTT_PWRGD#/PD
FSA.B.C
IREF
CPU[1:0]
REF[1:0]
CPU_ITP/SRC6
PLL1
SSC
N Programmable
ITP_EN
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
IREF
SRC[5:0]
48MHz
DOT96
PLL2
SSC
N Programmable
PLL3
PCI[5:0], PCIF[1:0]
SATA_SRC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2005 Integrated Device Technology, Inc.
DSC-6749/4
FEATURES:
One high precision PLL for CPU, with SSC and N program-
mable
One high precision PLL for SRC/PCI/SATA, SSC and N pro-
grammable
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Supports spread spectrum modulation, down spread 0.5%
Supports SMBus block read/write, index read/write
Selectable output strength for REF
Allows for CPU frequency to change to a higher frequency for
maximum system computing power
Enhanced capacitance on XTAL_IN and XTAL_OUT pins
Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV146 is a 56 pin clock device. The CPU output buffer is designed to
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced IREF to reduce the impact of VDD variation on differential
outputs, which can provide more robust system performance.
Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection,
which allows for isolated changes instead of affecting other clock groups.
OUTPUTS:
2*0.7V current –mode differential CPU CLK pair
6*0.7V current –mode differential SRC CLK pair, one
SATA_SRC pair
One CPU_ITP/SRC selectable CLK pair
6*PCI, two free running, 33.3MHz
1*96MHz, 1*48MHz
2*REF
KEY SPECIFICATIONS:
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
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