參數(shù)資料
型號(hào)： IDTIDT71P79604167BQI
廠商： Integrated Device Technology, Inc.
英文描述： 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
中文描述： 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2
文件頁(yè)數(shù)： 1/23頁(yè)
文件大?。?/td> 641K
代理商： IDTIDT71P79604167BQI
NOVEMBER 2005
DSC-6432/01
2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new famly of products
developed by Cypress Semconductor, IDT, and Mcron Technology,
Inc.
1
18Mb Pipelined
DDRII SIO SRAM
Burst of 2
IDT71P79204
IDT71P79104
IDT71P79804
IDT71P79604
Functional Block Diagram
Notes:
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
BW
is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
DATA
REG
ADD
REG
CTRL
LOGIC
CLK
GEN
(Note2)
SA
LD
R
/W
BW
x
(Note3)
K
K
C
C
SELECT OUTPUT CONTROL
W
S
O
O
WRITE DRIVER
(Note4)
(Note2)
CQ
CQ
Q
(Note1)
(Note4)
18M
MEMORY
ARRAY
DATA
REG
(Note1)
6432 drw 16
(Note1)
D
Description
The IDT DDRII
TM
Burst of two SIO SRAMs are high-speed syn-
chronous memories with independent, double-data-rate (DDR), read
and write data ports with two data items passed with each read or write.
Using independent ports for read and write data access, simplifies
systemdesign by elimnating the need for bi-directional buses. All buses
associated with the DDRII SIO are unidirectional and can be optimzed
for signal integrity at very high bus speeds. Memory bandwidth is higher
than DDR SRAMwith bi-directional data buses as separate read and
write ports elimnate bus turn around cycle. Separate read and write
ports also enable easy depth expansion. Each port can be selected
independantly with a R/
W
input shared among all SRAMs and provide
a new
LD
load control signal for each bank. The DDRII SIO has scal-
able output impedance on its data output bus and echo clocks, allowing
the user to tune the bus for low noise and high performance.
The DDRII SIO has a single SDR address bus with multiplexed
read and write addresses. The read/write and load control inputs are
received on the first half of the clock cycle. The byte and nibble write
signals are received on both halves of the clock cycle simultaneously
with the data they are controlling on the data input bus.
The DDRII SIO has echo clocks, which provide the user with a
clock that is precisely timed to the data output, and tuned with matching
impedance and signal quality. The user
can use the echo
clock for
downstreamclocking of the data. Echo clocks elimnate the need for the
user to produce alternate clocks with precise timng, positioning, and
signal qualities to guarantee data capture. Since the echo clocks are
Features
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
◆
Separate, Independent Read and Write Data Ports
- Supports concurrent transactions
◆
Dual Echo Clock Output
◆
2-Word Burst on all SRAMaccesses
◆
Multiplexed Address Bus
- One Read or one Write request per clock cycle
◆
DDR (Double Data Rate) Data Bus
- Two word burst data per clock
◆
Depth expansion through Control Logic
◆
HSTL (1.5V) inputs that can be scaled to receive signals from1.4V
to 1.9V.
◆
Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level from1.4V to 1.9V.
- Output Impedance adjustable from35 ohms to 70 ohms
◆
1.8V Core Voltage (V
DD
)
◆
165-ball, 1.0mmpitch, 15mmx 17mmfBGA Package
◆
JTAG Interface
相關(guān)PDF資料
PDF描述
IDTIDT71P79604200BQ 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604200BQI 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604250BQ 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDTIDT71P79604200BQ 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604200BQI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604250BQ 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604250BQI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79604267BQ 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
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