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參數(shù)資料
| 型號： | IDTQS3ST253Q8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | DUAL 4 LINE TO 1 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IDTQS3ST253Q8 |
9
IDTQS3ST253
HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIALTEMPERATURERANGE
IBH
+500
Sinking
Current
( + )
IBHL
IBH
IBHH
+60
+20
– 60
– 20
+60
IBHL
0.8V
2V
VIH
– 60 IBHL
VIL
Sourcing
Current
( – )
IBH
– 500
Vcc
+20 IBH
– 20 IBH
Voltage
VT
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
VT
≡≡≡≡≡ Threshold Voltage ≈ 1.5V
VIL
≈ .8
VIH
≈ 2V
ACTIVE TERMINATOR OR “BUS-HOLD” CIRCUIT
TheActiveTerminatorcircuit,alsoknownasthebus-holdcircuit,isconfiguredasa“weaklatch”withpositivefeedback. WhenconnectedtoaTTLorCMOS
input port, the bus-hold circuit holds the last logic state at the input when the input is “disconnected” from the driver. When the output of a device connected
to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit is that it prevents CMOS inputs
fromfloating,asituationwhichshouldbeavoidedtopreventspuriousswitchingofinputsandunnecessarypowerdissipation.Bus-holdisabettersolutionthan
thetraditionalapproachofusingresistiveterminationtoVccorGNDtopreventbusfloating,becausethebus-holdcircuitdoesnotconsumeanystaticpower.
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input voltage is
increased from 0 volts, the input “sink” current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the latch changes the
logicstateduetopositivefeedbackandthedirectionofthecurrentisreversed. AstheinputvoltageisfurtherincreasedtowardsVcc,theinput“source”current
begins to decrease, reaching the lowest level at VIN = Vcc.
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