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| 型號： | IEEE 802.11 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 69K |
| 代理商： | IEEE 802.11 |
2-1
TM
AN9810.1
2.4GHz Direct Sequence
Wireless LAN Cascade Analysis
Abstract
The paper describes the cascade
analysis of an IEEE 802.11 direct
sequence wireless LAN radio in the
2.4GHz ISM band. A step by step
approach is taken including: Basic
system architecture decisions, gain distribution/IF limiter
analysis and finally the complete cascade analysis.
Important RF parameters for each function block in both
the receive and transmit chains are evaluated and the
design trade-offs are explored.
Introduction
Wireless Local Area Network (WLAN) is coming onto the
marketplace with a flurry of products of various types and
designs. Wireless offers a different paradigm for computer
network users and capabilities breaking the tethers of the
wired only network. This paper will explore the process of
developing the architecture of one such WLAN system.
What should a WLAN radio do What are the needs of the
market place What performance is possible in the
technology Where should the compromise between cost and
performance be made These are the types of questions one
has to answer when setting goals for a new radio architecture.
Fortunately, the IEEE and the worldwide electronics industry
have had the foresight to develop the IEEE 802.11 standard to
limit the infinite range of possible combinations of
performance and protocol. This also provides the customer
with the bonus of compatibility between different vendors. The
IEEE 802.11 committee has created three standards for
wireless LAN communication; Frequency Hop (FH), Direct
Sequence (DS), and Infrared. The radio standards FH and DS
use two modulation methods that seem to attain similar goals,
but that offer special performance advantages in different
situations and applications.
This paper will analyze an example of a WLAN solution, a
Direct Sequence Spread Spectrum (DSSS) system from
Intersil Corporation, the PRISM chip set.
The Architecture
A basic architecture is shown in the block diagram in Figure
1. The radio design is centered on the expected signal
characteristics of the modulation method. A Differential
Quadrature Phase Shift Keying (DQPSK) modulation
encodes the data in terms of phase with minimal amplitude
variation, improving noise immunity. This is joined with the
IEEE 802.11 protocol standard Carrier Sense Multiple
Access/Collision Avoidance (CSMA/CA) and with the FCC
requirement for 10dB processing gain, to allow signals to
be received with approximately 0dB Signal to Noise Ratio
(SNR) for a 10
-5
Bit Error Rate (BER). The CSMA/CA
protocol allows only one user, per channel, at a time (i.e.,
first come, first serve) making for a quieter medium. The
processing gain, achieved by spreading the signal with a
PN code, allows a faint signal to be pulled from the noise
while suppressing non-correlating interferers.
A single antenna is used, although two antennas are
supported for diversity to counter the effects of multi-path
fading. From the antenna, the received input is applied to
the pre-select filter FL1. This filter is a two pole dielectric
design, rejecting interferers outside the 2.4GHz ISM band
and providing image rejection.
The T/R switch is integrated into the HFA3925 RF Power
Amplifier. The switch in receive mode leads to the HFA3424
Low Noise Amplifier, which is used to set the noise figure
for the entire receiver.
Next, the signal enters the HFA3624 RF/IF Converter, first
passing through the integrated LNA section and then going
off-chip to FL2. Filter FL2 is an inexpensive 2 pole monolithic
LC bandpass filter used to suppress image noise.
The signal then enters the downconverter section of the
HFA3624. Low-side local oscillator injection is used to mix
down to the single intermediate frequency, 280MHz. A
discrete LC matching network is used at the mixer output to
differentially combine the IF outputs, as well as impedance
match to a 50
environment.
The IF receive filter FL3, is a Surface Acoustic Wave (SAW)
device used for channel selection within the band. The
SAW output is reactively matched to the IF input of the
HFA3724 Quadrature IF Modulator/Demodulator.
In receive mode, the HFA3724 provides two limiting amplifiers,
a quadrature baseband demodulator, and two baseband low
pass filters. The two limiting amplifiers or limiters, in cascade
with a one pole LC limiter BPF FL4, provide most of the
receiver gain, giving the radio it’s sensitivity.
For engineers with an analog background, limiters can be
thought of as high speed, high gain comparators. They
operate on the largest signal present, amplifying it up to a
rail to rail output and thus rejecting smaller signals and
noise.
After the limiters, the signal is then mixed down to baseband
with the quadrature baseband demodulator into the I and Q
components. Finally anti-alias filtering is performed before
going to the analog to digital converters (ADCs) of the
Baseband Processor, HFA3824. The baseband circuit samples
the waveform with 3-bit ADCs and then despreads and
demodulates the received data.
Application Note
May 2000
Authors: Robert Rood, Doug Schultz
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
Intersil Corporation 2000
PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
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