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| 型號： | IMIB9948 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 39K |
| 代理商： | IMIB9948 |
B9940L
2.5V / 3.3V, 200 MHz, 1:18 Clock Distribution Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07105 Rev. **
5/24/2001
Page 4 of 7
AC Parameters
1
SYMBOL
Fmax
Tpd
PARAMETER
Maximum Input Frequency
PECL_CLK to Q Delay
2,4
MIN
TYP
MAX
200
4.0
5.2
3.8
4.4
55
150
200
1.4
2.2
1.2
1.7
850
750
1.1
UNITS
MHz
ns
CONDITIONS
2.0
2.6
1.8
2.3
45
3.5
4.0
3.3
3.8
VDD = 3.3V
VDD = 2.5V
VDD=3.3V
VDD = 2.5V
Measured at VDDC/2
VDD=3.3V, Fin = 150MHz
VDD=2.5V, Fin = 150MHz
PECL, VDDC = 3.3V
PECL, VDDC = 2.5V
TCLK, VDDC = 3.3V
TCLK, VDDC = 2.5V
PECL_CLK
TCLK
0.7V to 2.0V,
VDDC = 3.3V
0.5V to 1.8V,
VDDC = 2.5V
Tpd
TTL_CLK to Q Delay
2,4
ns
FoutDC
Tskew
Output Duty Cycle
2,3,4
Output-to-Output Skew
2,4
%
ps
Tskew(pp)
Part-to-Part Skew
5
ns
Tskew(pp)
Part-to-Part Skew
5
ns
Tskew(pp)
Part to Part Skew
6
ps
0.3
Tr / Tf
Output Clocks Rise / Fall Time
2,4
0.3
1.2
ns
VDD = 3.3V
±
5% or 2.5V
±
5%, VDDC = 3.3V
±
5% or 2.5V
±
5%, TA = -40
°
C to +85
°
C
Note 1:
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2:
Outputs driving 50
transmission lines.
Note 3:
50% input duty cycle.
Note 4:
Outputs loaded with 30pF each
Note 5:
Across temperature and voltage ranges, includes output skew
Note 6:
For a specific temperature and voltage, includes output skew
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