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| 型號(hào)： | IMST414B-J20S |
| 英文描述： | Peripheral IC |
| 中文描述： | 外圍芯片 |
| 文件頁(yè)數(shù)： | 16/74頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | IMST414B-J20S |
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IMS T400
/ 74
16
256K
Dynamic
RAM
4
256K
Dynamic
RAM
4
4
256K
Dynamic
RAM
ClockIn
(5MHz)
Link0In
notMemWrB2
notMemWrB1
notMemWrB0
notMemRd
notMemS3
notMemS2
notMemS1
notMemS0
notRAS
notCAS
notOE
CapPlus
CapMinus
256K
Dynamic
RAM
4
M
M
M
M
M
M
M
M
M
M
M
Link0Out
Link1In
Link1Out
MemConfig
As Link0
56R
GND
IMS
T400
Column
address
latch
Row/
column
address
multiplexor
notMemWrB3
VDD
GND
100K
M
Figure 5.2
IMS T400 dynamic RAM application
5.1.10
MemReq, MemGranted
Direct memory access (DMA) can be requested at any time by driving the asynchronous
MemReq
input
high.
MemGranted
follows the timing of the bus being tristated and can be used to signal to the device
requesting the DMAthat it has control of the bus.Note that
MemGranted
changes on the falling edge of
ProcClockOut
and can therefore be sampled to establish control of the bus on the rising edge of
ProcClockOut
.
5.1.11
MemConfig
MemConfig
is aninput pin used toreadconfiguration datawhen setting external memory interface(EMI)
characteristics.
5.1.12
ProcClockOut
This clock is derived from the internal processor clock, which is in turn derived from
ClockIn
. Its period
is equal to one internal microcode cycle time, and can be derived from the formula
TPCLPCL
=
TDCLDCL
/
PLLx
where
TPCLPCL
is the
ProcClockOut Period
,
TDCLDCL
is the
ClockIn Period
and
PLLx
is the phase
lock loop factor for the relevant speed part, obtained from the ordering details (Ordering section).
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| IMST425G20S | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Peripheral IC |
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