參數(shù)資料
型號： IMST425-G17S
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁數(shù)： 34/74頁
文件大?。?/td> 563K
代理商： IMST425-G17S
IMS T400
/ 74
34
Addresses #7FFFFFEC to #7FFFFFF4 (fields 11and 12) define the refresh interval and whether refresh
is to be used, whilst the final address (field 13) supplies a high bit to
MemConfig
if a late write cycle is
required.
The columns to the rightof the coding table show thevalues of each configuration bit for thefour sample
external configuration diagrams. Note the inclusion of period
E
at the end of
T6
in some diagrams. This
isinsertedtobringthestartofthenext
TstateT1
to coincidewitha risingedgeof
ProcClockOut
(page 16).
Waitstates
W
have beenaddedto showtheeffectofthem onstrobe timing;theyarenotpartofa configura-
tion. In each case which includes wait states,two wait periods are defined. This shows that if a wait state
would causethe start of
T5
to coincide with a fallingedge of
ProcClockOut
, another period
Tm
is gener-
ated by theEMI to forceit tocoincide with a risingedgeof
ProcClockOut
.Thiscoincidenceisonly neces-
sary if wait states are added, otherwise coincidence with a falling edge is permitted. Any configuration
memory access is only permitted to be extended using wait, up to a total of 14
ClockIn
periods.
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