參數(shù)資料
型號(hào)： IMST425-G17S
元件分類(lèi)： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 39/74頁(yè)
文件大?。?/td> 563K
代理商： IMST425-G17S
6 Events
/ 74
39
6
Events
EventReq
and
EventAck
provide an asynchronous handshakeinterface betweenan external eventand
an internal process.When anexternal event takes
EventReq
high theexternal event channel (additional
to theexternallinkchannels) ismadereadyto communicate witha process.Whenboththeevent channel
and the process are ready the processor takes
EventAck
high and theprocess, if waiting, is scheduled.
EventAck
is removed after
EventReq
goes low.
EventWaiting
is assertedhighby thetransputer whena process executesan inputon theevent channel;
typically with the occam
EVENT ANY
instruction. It remains high whilst the transputer is waiting for or
servicing
EventReq
and isreturned lowwhen
EventAck
goes high.The
EventWaiting
pinchanges near
the falling edge of
ProcClockOut
and can therefore be sampled by the rising edge of
ProcClockOut
.
The
EventWaiting
pin can only be asserted by executing an in instruction on the event channel. The
EventWaiting
pin isnotassertedhighwhenanenablechannel (enbc)instructionisexecutedontheEvent
channel (during an ALT construct inoccam, for example). The
EventWaiting
pin can be asserted by ex-
ecuting the occam input onthe event channel (such as
Event ANY
), providedthat this does not occur
as a guard in analternative process.The
EventWaiting
pin can notbe used to signify that an alternative
process (ALT) is waiting on an input from the event channel.
EventWaiting
allows a process to control external logic; for example, to clock a number of inputs into a
memorymapped datalatchso thattheevent requesttypecanbedetermined.Thisfunctionisnotavailable
on the IMS T414 and IMS T800.
Only one process may use the event channel at any given time. If no process requires an event to occur
EventAck
will never be taken high. Although
EventReq
triggers the channel on a transition from low to
high, itmust not be removedbefore
EventAck
is high.
EventReq
should be lowduring
Reset
;if notit will
be ignored until it has gone low and returned high.
EventAck
is taken low when
Reset
occurs.
If the process is a high priority one and no other high priority process is running, typical latency is 19 full
processorcycles
TCPLCPL
(38
Tm
), and maximumlatency(assumingall memoryaccessesareinternal)
is 58 full processor cycles (116
Tm
). Setting a high priority task to wait for an eventinput allows theuser
to interrupt a transputer program running at low priority. The time taken from asserting
EventReq
to the
execution of the microcode interrupt handler in the CPU is four cycles. The followingfunctions takeplace
during the four cycles:
Cycle 1
Sample
EventReq
at pad on the rising edge of
ProcClockOut
and synchronise.
Cycle 2
Edge detect the synchronised
EventReq
and form the interrupt request.
Cycle 3
Sample interrupt vector for microcode ROM in the CPU.
Cycle 4
Execute the interrupt routine for Event rather than the next instruction.
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