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| 型號： | IMST425-J20S |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 64/74頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IMST425-J20S |
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IMS T400
/ 74
64
The
DEF
column of the tablesindicates thedescheduling/error features of an instruction as described in
table .
Ident
D
E
F
applies to IMS T805 only
Feature
The instruction is a descheduling point
The instruction will affect the
Error
flag
The instruction will affect the
FP_Error
flag
See section:
11.2
11.3
11.6
Table 11.5
Instruction features
11.2
Descheduling points
The instructions in table 11.6are the only ones at which a process may be descheduled. They are also
the ones at which the processor will halt if the
Analyse
pin is asserted (refer to
Analyse
section).
input message
timer alt wait
jump
output message
timer input
loop end
output byte
stop on error
end process
output word
alt wait
start process
Table 11.6
Descheduling point instructions
11.3
Error instructions
The instructionsin table 11.7are theonlyones whichcanaffecttheErrorflag directly.Note, however, that
the floatingpoint uniterrorflagFP_Errorisset bycertain floatingpoint instructions(section 11.6),and that
Error can be set from this flag by fpcheckerror
add
multiply
long add
set error
check word
does not apply to IMS T225
applies to IMS T805 only
add constant
fractional multiply
long subtract
testerr
check subscript from 0
subtract
divide
long divide
fpcheckerror
check single
remainder
check count from 1
Table11.7
Error setting instructions
11.4
Debugging support
Table 11.20 (page 70) contains a number of instructions to facilitate the implementation of breakpoints.
These instructions overload the operation of j0. Normally j0 is a no-op which might cause descheduling.
Setj0breakenables the breakpointing facilities and causes j0to act as a breakpointing instruction. When
breakpointing is enabled, j0swaps the current
Iptr
and
Wptr
with an
Iptr
and
Wptr
stored aboveMemS-
tart. Thebreakinstructiondoes notcause descheduling,andpreserves thestateof theregisters. Itis pos-
sible to single step the processor at machine level using these instructions. Refer to Support for debug-
ging/breakpointing in transputers(technical note 61) for more detailed information regarding debugger
support.
11.5
Block move
The blockmove instructions(Table11.21) move any number of bytesfrom anybyte boundary inmemory,
toanyotherbyteboundary, usingthesmallestpossible numberof wordread,andwordorpart-wordwrites.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IMST425-J25S | 32-Bit Microprocessor |
| IMST425-X25S | 32-Bit Microprocessor |
| IMST800C-G17S | Peripheral IC |
| IMST800C-G20S | Peripheral IC |
| IMST800C-G30S | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMST425-J25S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| IMST425-X25S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
| IMST800C-G17S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST800C-G20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| IMST800C-G30S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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