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11 Transputer instruction set summary
/ 74
71
Operation
Code
74
75
Memory
Code
27F4
27F5
Mnemonic
Processor
Cycles
35
11
Name
DEF
crcword
crcbyte
calculate crc on word
calculate crc on byte
76
77
78
27F6
27F7
27F8
bitcnt
bitrevword
bitrevnbits
b
+2
36
n
+4
count bits set in word
reverse bits in word
reverse bottom n bits in word
Table 11.22
CRC and bit operation codes
11.8
Floating point instructions
11.9
Floating point instructions for IMS T805 only
Operation
Code
8E
8A
86
82
9F
A0
AA
A6
AC
A8
88
84
9E
Memory
Code
28FE
28FA
28F6
28F2
29FF
2AF0
2AFA
2AF6
2AFC
2AF8
28F8
28F4
29FE
Mnemonic
Processor
Cycles
2
3
4
6
2
2
8/11
9/12
13/20
21/30
2
3
4
Name
DEF
fpldnlsn
fpldnldb
fpldnlsni
fpldnldbi
fpldzerosn
fpldzerodb
fpldnladdsn
fpldnladddb
fpldnlmulsn
fpldnlmuldb
fpstnlsn
fpstnldb
fpstnli32
fp load non-local single
fp load non-local double
fp load non-local indexed single
fp load non-local indexed double
load zero single
load zero double
fp load non local & add single
fp load non local & add double
fp load non local & multiply single
fp load non local & multiply double
fp store non-local single
fp store non-local double
store non-local int32
F
F
F
F
Processor cycles are shown as
Typical/Maximum
cycles.
Table 11.23
Floating point load/store operation codes
Operation
Code
AB
A4
A3
Memory
Code
2AFB
2AF4
2AF3
Mnemonic
Processor
Cycles
1
1
1
Name
DEF
fpentry
fprev
fpdup
floating point unit entry
fp reverse
fp duplicate
Table 11.24
Floating point general operation codes