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參數(shù)資料
| 型號(hào)： | IN74AC109 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| 中文描述： | 雙JK觸發(fā)器的設(shè)置和復(fù)位高速硅柵CMOS |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 170K |
| 代理商： | IN74AC109 |
IN74AC109
118
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
V
IN
V
OUT
I
IN
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±
20
±
50
±
50
750
500
V
DC Output Voltage (Referenced to GND)
V
DC Input Current, per Pin
mA
I
OUT
DC Output Sink/Source Current, per Pin
mA
I
CC
DC Supply Current, V
CC
and GND Pins
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
mW
Tstg
Storage Temperature
-65 to +150
°
C
°
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
°
C from 65
°
to 125
°
C
SOIC Package: : - 7 mW/
°
C from 65
°
to 125
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
T
J
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
140
V
°
C
°
C
mA
Junction Temperature (PDIP)
T
A
Operating Temperature, All Package Types
-40
+85
I
OH
I
OL
t
r
, t
f
Output Current - High
-24
Output Current - Low
Input Rise and Fall Time
*
(except Schmitt Inputs)
24
mA
V
CC
=3.0 V
V
CC
=4.5 V
V
CC
=5.5 V
0
0
0
150
40
25
ns/V
*
V
IN
from 30% to 70% V
CC
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
≤
(V
IN
or V
OUT
)
≤
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IN74AC109D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| IN74AC109N | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| IN74AC112 | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| IN74AC112D | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
| IN74AC112N | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS |
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