參數(shù)資料
型號(hào)： INTEL387DX
英文描述： Intel387 DX - MATH COPROCESSOR
中文描述： Intel387霉素-數(shù)學(xué)協(xié)處理器
文件頁(yè)數(shù)： 20/41頁(yè)
文件大?。?/td> 435K
代理商： INTEL387DX
Intel387
TM
DX MATH COPROCESSOR
3.1.1 Intel386
TM
DX CPU CLOCK 2 (CPUCLK2)
This input uses the Intel386 DX CPU CLK2 signal to
time the bus control logic. Several other MCP sig-
nals are referenced to the rising edge of this signal.
When CKM
e
1 (synchronous mode) this pin also
clocks the data interface and control unit and the
floating-point unit of the MCP. This pin requires
MOS-level input. The signal on this pin is divided by
two to produce the internal clock signal CLK.
3.1.2 Intel387
TM
DX MCP CLOCK 2 (NUMCLK2)
When CKM
e
0 (asynchronous mode) this pin pro-
vides the clock for the data interface and control unit
and the floating-point unit of the MCP. In this case,
the ratio of the frequency of NUMCLK2 to the fre-
quency of CPUCLK2 must lie within the range 10:16
to 14:10. When CKM
e
1 (synchronous mode) this
pin is ignored; CPUCLK2 is used instead for the data
interface and control unit and the floating-point unit.
This pin requires TTL-level input.
3.1.3 Intel387
TM
DX MCP CLOCKING MODE
(CKM)
This pin is a strapping option. When it is strapped to
V
CC
, the MCP operates in synchronous mode; when
strapped to V
SS
, the MCP operates in asynchronous
mode. These modes relate to clocking of the data
interface and control unit and the floating-point unit
only; the bus control logic always operates synchro-
nously with respect to the Intel386 DX Microproces-
sor.
240448–7
Figure 3.2. Asynchronous Operation
20
20
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