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參數(shù)資料
| 型號(hào)： | IOS62C256-70U |
| 英文描述： | IC-SM-256K CMOS SRAM |
| 中文描述： | 集成電路的Sm - 256K CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 7/7頁(yè) |
| 文件大小： | 65K |
| 代理商： | IOS62C256-70U |
ISSI
IS62C256
Integrated Silicon Solution, Inc.
Rev. D 0895
SR81995C256
2-7
WRITE CYCLE NO. 2 (
CE
Controlled)
(1,2)
ORDERING INFORMATION
Commerical Range: 0
°
C to +70
°
C
Speed
(ns)
Order Part No.
Package
45
45
45
IS62C256-45W
IS62C256-45T
IS62C256-45U
600-mil Plastic DIP
TSOP
450-mil Plastic SOP
70
70
70
IS62C256-70W
IS62C256-70T
IS62C256-70U
600-mil Plastic DIP
TSOP
450-mil Plastic SOP
100
100
100
IS62C256-100W
IS62C256-100T
IS62C256-100U
600-mil Plastic DIP
TSOP
450-mil Plastic SOP
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE
t
SA
t
HA
t
PWE
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
D
IN
CE
WE
D
OUT
ORDERING INFORMATION
Industrial Range: –40
°
C to +85
°
C
Speed
(ns)
Order Part No.
Package
45
45
45
IS62C256-45WI
IS62C256-45TI
IS62C256-45UI
600-mil Plastic DIP
TSOP
450-mil Plastic SOP
70
70
70
IS62C256-70WI
IS62C256-70TI
IS62C256-70UI
600-mil Plastic DIP
TSOP
450-mil Plastic SOP
100
100
100
IS62C256-100WI 600-mil Plastic DIP
IS62C256-100TI
TSOP
IS62C256-100UI
450-mil Plastic SOP
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
800-379-4774
Fax: 408-588-0806
E-mail: sales@issiusa.com
Web: www.issiusa.com
ISSI
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE
≥
V
IH
.
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