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參數(shù)資料
| 型號(hào)： | IP113M |
| 英文描述： | Managed 10/100Base-TX / FX Media Converter |
| 中文描述： | 托管個(gè)10/100Base-TX /外匯收發(fā)器 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大?。?/td> | 186K |
| 代理商： | IP113M |
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IP113
PIN Description
(continued)
Functional Description
Basic Operation
Preliminary, Specification subject to change without notice
IP113-DS-P07
Jul. 19, 2002
10
IP113 consists of two switching ports. Full/half duplex
and speed of TP port depends on the result of auto
negotiation. It is not necessary to use an external
memory to buffer packets.
Each port in IP113 has its own receive buffer
management, transmit buffer management, transmit
queue management, transmit MAC and receive MAC. All
ports share a hashing unit, a memory interface unit, an
empty buffer management, and an address table.
An incoming packet is stored in the internal memory if
the packet is error free. A packet is error free if its CRC
field is correct and its length is between 64 and 1536
byte. At the same time, IP113 examines the address field
of the packet. By the way, switch learns the locations of
every station (source address) and records them on the
address table. IP113 then reads the packet from the
internal memory and sends it to the other ports according
to the address table. Eventually, IP113 supports the
switching function by dropping or forwarding the
incoming packets.
Block Description
The basic function of each block in the block diagram is
illustrated in the following context. Hashing unit is
responsible to learn and to recognize address. Transmit
buffer management and receive buffer management are
responsible to store data to or to read data from the
internal memory through memory interface unit. Transmit
MAC and receive MAC interface to transceivers and
implement Ethernet protocol.
Receive MAC receives the incoming data from
transceiver and converts nibble data into double word
data. As a 32 bit data is ready, it feeds the data into
receive FIFO and requests receive buffer management
for data transfer. When receive buffer management
receives the request, it gets a empty block from empty
buffer management and writes the double word data to
the buffer, which is located in the internal SSRAM,
through memory interface unit. The incoming packet is
fed to hashing unit at the same time. Hashing unit
extracts the source address of incoming packet to set up
an address table. An incoming packet is dropped or
forwarded according to the table. The address table is
built in the SSRAM of IP113.
All ports share an empty buffer management. After reset,
the empty buffer management provides 2 addresses of
empty blocks. When a packet comes in, it searches for a
new empty block. After a packet is forwarded, the
corresponding blocks are released. Empty buffer
management treats the block as an empty block and
provides its address to desired receive buffer
management. Two addresses are always ready for
receive buffer management.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP113MLF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 10/100Base-TX / FX Media Converter |
| IP113MLF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 10/100Base-TX / FX Media Converter |
| IP113MLF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 10/100Base-TX / FX Media Converter |
| IP113MLF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 10/100Base-TX / FX Media Converter |
| IP113MLF-DS-R04 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 10/100Base-TX / FX Media Converter |
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