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參數(shù)資料
| 型號： | IQ80C154-L16 |
| 英文描述： | CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| 中文描述： | 的CMOS 0至36 MHz的單芯片8位微控制器 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 354K |
| 代理商： | IQ80C154-L16 |
Rev.F (14 Jan. 97)
11
MATRA MHS
In this mode, T32 = 0 and C/T0 = 1. Before it can
make an increment, the 83C154
μ
must detect two
transitions on its T0 input. As shown in figure 14,
input T0 is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC
÷
12.
Figure 13. Counter Incrementation Condition.
The counter will only evolve if a level 1 is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
Watchdog Mode
WDT = 1 enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and 1, of which
the overflows act on TF1 (TF1 = 1), activate the
WATCHDOG Mode.
Figure 14. The Different Watchdog Configurations.
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