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參數(shù)資料
| 型號： | IR22381QPBF |
| 廠商： | International Rectifier |
| 英文描述： | 3-PHASE AC MOTOR CONTROLLER IC |
| 中文描述： | 3相AC電機(jī)控制IC |
| 文件頁數(shù)： | 26/30頁 |
| 文件大小： | 1133K |
| 代理商： | IR22381QPBF |
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IR22381Q
PBF
/IR21381Q
(
P
b
F
)
26
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor R
Goff
is
when the collector of the IGBT in off state is forced
to commutate by external events (i.e. the turn-on of
the companion IGBT).
In this case the dV/dt of the output node induces a
parasitic current through C
RESoff
flowing in R
Goff
and
R
DRn
(see Figure 26).
If the voltage drop at the gate exceeds the threshold
voltage of the IGBT, the device may self turn on
causing large oscillation and relevant cross
conduction.
OFF
HS Turning ON
ON
dV/dt
R
Goff
C
RESoff
R
DRn
C
IES
Figure 26:
R
Goff
sizing: current path when Low
Side is off and High Side turns on
The transfer function between IGBT collector and
IGBT gate then becomes:
(
DRn
Goff
ge
R
R
s
V
+
+
Which yields to a high pass filter with a pole at:
1
/
RESoff
DRn
Goff
C
R
R
+
)
(
)
(
1
)
IES
RESoff
DRn
Goff
RESoff
de
C
C
C
R
R
s
V
+
+
=
)
(
)
(
IES
C
+
=
τ
As a result, when
τ
is faster than the collector rise
time (to be verified after calculation) the transfer
function can be approximated by:
V
+
=
)
(
RESoff
DRn
Goff
de
ge
C
R
R
s
V
So that
dt
dV
C
R
R
V
de
RESoff
DRn
Goff
ge
+
=
)
(
in the
time domain.
Then the condition:
(
)
dt
dV
C
R
R
V
V
out
RESoff
DRn
Goff
ge
th
+
=
>
must be verified to avoid spurious turn on.
Rearranging the equation yields:
V
R
(1)
DRn
RESoff
th
Goff
R
dt
dV
C
<
In any case, the worst condition for a spurious turn
on is with very fast steps on IGBT collector.
In that case collector to gate transfer function can
be approximated with the capacitor divider:
C
V
V
+
which is driven only by IGBT characteristics.
As an example, table 3 reports R
Goff
(calculated with
the above mentioned equation (1)) for two popular
IGBTs to withstand
dV
out
/dt = 5V/ns
.
NOTICE:
the above-described equations are
intended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and
parasitic component dependent on the PCB and
power section layout and related connections.
)
(
IES
RESoff
RESoff
de
ge
C
C
=
Table 1: R
Gon
sizing driven by t
sw
constraint
IGBT
Qge
Qgc
Vge*
tsw
Iavg
Rtot
RGon
→
std commercial value
Tsw
GB15XP120K*
GB05XP120K
IRGB5B120KD
12nC
3.7nC
3.7nC
46nC
14nC
13nC
9V
9.5V
9.5V
500ns
400ns
500ns
116mA
44mA
33mA
77
124
164
Rtot - RDRp = 15
→
10
Rtot - RDRp = 65
→
68
Rtot - RDRp = 102
→
100
→
465ns
→
408ns
→
502ns
Table 2: Table 2: RGon sizing driven by dVOUT/dt constraint
IGBT
Qge
Qgc
Vge*
CRESoff
Rtot
RGon
→
std commercial value
Rtot - RDRp = 4.5
→
4.7
Rtot - RDRp = 48.8
→
47
Rtot - RDRp = 57
→
56
dVout/dt
GB15XP120K*
GB05XP120K
IRGB120KD
12nC
3.7nC
3.7nc
46nC
14nC
13nC
9V
9.5V
9.5V
38pF
12pF
11pF
47
91
100
→
5V/ns
→
5.1V/ns
→
5V/ns
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