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參數(shù)資料
| 型號： | IR3086MTR |
| 廠商： | International Rectifier |
| 英文描述： | PHASE IC WITH OVP, FAULT AND OVERTEMP DETECT |
| 中文描述： | 相位IC帶OVP，故障及超溫檢測 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 417K |
| 代理商： | IR3086MTR |
IR3086
Page 8 of 15
9/1/03
R
C
CLK1
VVALLEY (1.00V)
P
VPHASE1&8 (1.5V)
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE4&5 (4.5V)
VPEAK (5.0V)
CLK2
50% RAMP
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
SLOPE = 80mV / % DC
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
Figure 3 – 8 Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the PWMRMP
voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. When the
PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the high side driver,
turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the PWMRMP
capacitor to the VDAC voltage of the Control IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase
with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input range of the
PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement
guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It also favors
response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The
inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements.
An additional advantage is that differences in ground or input voltage at
the phases have no effect on operation since the PWM ramps are referenced to VDAC.
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