![](http://datasheet.mmic.net.cn/30000/MR80C32-20-D_datasheet_2377239/MR80C32-20-D_130.png)
130
8154B–AVR–07/09
ATmega16A
17.10 Timer/Counter Prescaler
Figure 17-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
T2S. clkT2S is by default connected to the main
system I/O clock clk
IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Apply-
ing an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
T2S/8, clkT2S/32, clkT2S/64,
clk
T2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
caler. This allows the user to operate with a predictable prescaler.
17.11 Register Description
17.11.1
TCCR2 – Timer/Counter Control Register
Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2 is written when
operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate compare
match is forced on the waveform generation unit. The OC2 output is changed according to its
COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOSC1
AS2
CS20
CS21
CS22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSR2
Clear
clk
T2
Bit
7
65
432
1
0
FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
TCCR2
Read/Write
W
R/W
Initial Value
0