
IS23SC1604
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
NV002-0D
01/19/99
ISSI
IS23SC1604 OPERATIONS
Power-On Reset (POR)
When the supply voltage is first applied to the device, the
device initiates POR. All the internal flags are clear (refer to
Definition of IS23SC1604 Internal Flags ), and the internal
address counter is reset to zero.
Reset
With CLK LOW, a HIGH-to-LOW transition at RST resets
the address counter to zero. After the falling edge of RST,
the device outputs the first bit of the memory on I/O pin. The
reset operation will have no effect on any internal flags (see
Figure 3).
Addressing
Addressing is handled by an internal address counter which
is incremented on the falling edge of CLK. When the counter
continues to increment past 16383, the counter will roll over
back to zero. The counter can also be cleared to zero by the
reset operation.
Read
If read access to a memory bit is enabled, the state of the
bit can be read out of the device by incrementing the
address counter to the bit location. The device outputs the
state of the read bit on the I/O pin after the falling edge of
the last clock pulse that increments the address counter to
the read bit location. However, if the read access to the
memory bit is inhibited, the state of the data bit will not be
output and the I/O pin will be placed in high-impedance
state ‘1’ (see Figure 4).
Compare
Compare operation allows users to input the security/erase
key code for the security/erase key code validation for read/
write/erase access to protected application zones (refer to
Security/Erase Key Code Validation Operation).
The compare operation latches the user’s input Security/
Erase Key bit into the device at the rising edge of CLK and
the bit comparison is performed on the next falling edge of
CLK. The compare and read operations are executed in the
same manner. The device distinguishes between the two
operations by testing the address counter for security/erase
key code location and the state of corresponding security/
erase key code valid comparison flag (see Figure 5).
Write
If write access to a memory bit is enabled, the content of the
bit can be written over with a ‘0’ value by performing the
following sequence: select PGM (logic HIGH state), input ‘0’
on the I/O pin, change CLK from LOW-to-HIGH, deselect
PGM (logic LOW state), wait for 5 ms programming delay,
and then bring CLK down from HIGH-to-LOW to complete
the write operation. The new state of the bit will be output at
the end of the write operation after the falling edge of CLK
for data verification (see Figure 6).
Erase
If erase access to a memory bit is enabled, the content of the
bit can be written over with a ‘1’ value with the erase
operation. Although erase is performed on single bits, the
erase operation writes FFH to the whole byte which contains
the erased bits because the memory is organized into 8-bit
bytes. The erase operation can be executed by performing
the following sequence: select PGM (logic HIGH state),
input ‘1’ on the I/O pin, change CLK from LOW-to-HIGH,
deselect PGM (logic LOW state), wait for 5 msec
programming delay, and then bring CLK down from HIGH-
to-LOW to complete the erase operation. The new state of
the bit will be output at the end of the erase operation after
the falling edge of CLK for data verification (see Figure 6).