參數(shù)資料
型號(hào): IS24C01-3
廠商: Integrated Silicon Solution, Inc.
英文描述: Low Cost 1024-Bit Serial EEPROM.(低價(jià) 1K 串行EEPROM)
中文描述: 低成本1024位串行EEPROM。(低價(jià)一千串行EEPROM的)
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 88K
代理商: IS24C01-3
ISSI
IS24C01-3
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EP013-0A
04/17/98
PIN DESCRIPTIONS
Serial Clock (SCL) -
The SCL input is used to clock all data
into and out of the device. In the WRITE mode, data must
remain stable when SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) -
The SDA pin is a bidirectional pin used
to transfer data into and out of the device. Data may
change only when SCL is LOW. It is an open-drain output,
and may be wire-ORed with any number of open-drain or
open-collector outputs.
A0, A1, and A2 -
The address inputs are used to set the
least significant three bits of the slave address. These
inputs may be tied HIGH or LOW, or they may be actively
driven. These inputs allow up to eight IS24C01-3 devices
to be connected together on the bus.
Write Control (
disable any attempt to write to the memory. When HIGH,
the memory is protected; when LOW, the write function is
normal. The part can be read independent of the state of
WC
pin. When not connected this pin will be pulled LOW.
WC
)
- The Write Control input is used to
ENDURANCE AND DATA RETENTION
The IS24C01-3 is designed for applications requiring high-
endurance write cycles and unlimited read cycles. It
provides 10 years of secure data retention, with or without
power applied, after the execution of 100K write cycles.
APPLICATIONS
The IS24C01-3 is ideal for high volume applications
requiring low power and low density storage. This device
uses a low-cost, space-saving 8-pin plastic package.
Candidate applications include robotics, alarm devices,
electronic locks, meters and instrumentation.
PIN CONFIGURATION
8-Pin DIP and SOIC
PIN DESCRIPTIONS
A0-A2
Address Inputs
SDA
Serial Data I/O
SCL
Serial Clock Input
WC
Write Control Input
Vcc
Power
GND
Ground
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WC
SCL
SDA
GENERAL DESCRIPTION
The IS24C01-3 features a SERIAL communication, and
supports bidirectional data transmission protocol allowing
operation on a simple two-wire bus between the different
devices connected somewhere on the system bus. The
two-wire bus was defined as a serial data line (SDA), and
a serial clock line (SCL). (Refer to Figure 1. Typical System
Bus Configuration.)
The protocol defines any device that sends data onto the
SDA bus as a transmitter, and the receiving device as a
receiver. The device controlling the data transmission is
named MASTER device, and the controlled device is
named SLAVE device. In all cases, the IS24C01-3 will be
a slave device, since it never initiates any data transfers.
Up to eight IS24C01-3 can be connected to the bus.
Device's physical address inputs A0-A2 must be connected
to either Vcc or GND.
Following a START condition, the MASTER (transmitter)
device must initiate the “Device Addressing Byte” including
device type identifier, device address, and a read or write
operation to select a slave device (receiver) connected to
the system bus. The receiver will then respond with an
ACKnowledge by pulled the SDA line LOW.
The ACKnowledge is used to indicate successful data
transfers. The transmitting device will release the data bus
(SDA goes HIGH) after transmitting eight bits (one data bit
is transfered at the falling edge of each clock cycle). During
the ninth clock cycle, the receiver will pull the SDA line
LOW to ACKnowledge the transmitter that it received the
eight bits of data. (Refer to Figure 2. ACKnowledge
Response from Receiver Diagram.)
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