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參數(shù)資料
| 型號： | IS24C01-3 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | Low Cost 1024-Bit Serial EEPROM.(低價 1K 串行EEPROM) |
| 中文描述： | 低成本1024位串行EEPROM。（低價一千串行EEPROM的） |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 88K |
| 代理商： | IS24C01-3 |
ISSI
IS24C01-3
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
EE013-0A
04/17/98
3
Page Write
The IS24C01-3 is capable of 8-byte page- WRITE operation.
A page-WRITE is initiated in the same manner as a byte
write, but instead of terminating the internal write cycle
after the first data word is transfered, the master device
can transmit up to 7 more words. After the receipt of each
data word, the IS24C01-3 responds immediately with an
ACKnowledge on SDA line, and the three lower order data
word address bits are internally incremented by one while
the higher order bits of the data word address remain
constant. If the master device should transmit more than 8
words, prior to issuing the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. All inputs are disabled until completion of
the internal WRITE cycle. (Refer to Figure 6. Write Operation
for the Address, ACKnowledge, and Data Transfer
Sequence.)
Acknowledge Polling
Once the internal write cycle has started and the
IS24C01-3 inputs are disabled, acknowledge polling can
be initiated. This involves sending a start condition followed
by the Device Addressing Byte. The read/write bit is
representive of the operation desired. Only if the internal
write cycle has been completed will the IS24C01-3 respond
with an acknowledge on the SDA bus allowing the read or
write sequence to continue.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
device addressing byte is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24C01-3 contains an internal address counter which
maintains the address of the last data word accessed,
incremented by one. For example, if the previous operation
either a read or write operation addressed to the address
location n, the internal address counter would address to
address location n+1. When the IS24C01-3 receives the
Device Addressing Byte with a READ operation (read/
write bit set to “1”), it will respond an ACKnowledge and
transmit the 8-bit data word stored at address location n+1.
If the Current Address READ operation only accesses a
single byte of data, the master device terminates the
Current Address READ operation by pulling ACKnowledge
HIGH (lack of ACKnowledge) indicating the last data word
to be read, followed by a STOP condition.
(Refer to Figure 7. Current Address Read Diagram.)
DEVICE OPERATION
START and STOP Conditions
Both SDA and SCL lines remain HIGH when the SDA bus
is not busy. A HIGH-to-LOW transition of SDA line, while
SCL is HIGH, is defined as the START condition. A LOW-
to-High transition of SDA line, while SCL is HIGH, is
defined as STOP condition. (Refer to Figure 3. Start and
Stop Conditions.)
Data Validity Protocol
One data bit is transferred during each clock cycle. The
data on the SDA line must remain stable during the HIGH
period of the clock cycle, because changes on SDA line
during the SCL HIGH period will be interpreted as START
or STOP control signals. (Refer to Figure 4. Data Validity
Protocol.)
Device Addressing Byte Definitions
The most significant four bits of Device Addressing Byte
(Bit 7 to Bit 4) are defined as the device type identifier. For
IS24C01-3, this is fixed as 1010. The next three significant
address bits (Bit 3 to Bit 1) address a particular device. Up
to eight IS24C01-3 devices can be connected on the bus.
These eight addresses are defined by the state of the A0,
A1, and A2 inputs. The last bit Bit 0 defines the write or read
operation to be performed. When set to “1”, a READ
operation is selected; when set to “0” a WRITE operation
is selected. (Refer to Figure 5. Device Addressing Byte
Definitions.)
WRITE OPERATION
Byte Write
For a WRITE operation, the IS24C01-3 requires another
Byte and ACKnowledgement. This data word address
provides access to any one of the 256 data words of
device's memory array.
Upon receipt of the data word address, the IS24C01-3
responds with an ACKnowledge on SDA, and waits for the
next 8-bit data word, then again responding with an
ACKnowledge. The master device terminates the Byte
Write Operation by generating a STOP condition, afterward
the IS24C01-3 begins the internal WRITE cycle to the
nonvolatile memory array. Refer to Write Cycle Timing. All
inputs are disabled during this write cycle and the device
will not response to any requests from the master. (Refer
to Figure 6. Write Operation for the Address, ACKnowledge,
and Data Transfer Sequence.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS24C01-3G | 功能描述:電可擦除可編程只讀存儲器 2.5V 1Kb RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| IS24C01-3GA | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM |
| IS24C01-3GI | 功能描述:電可擦除可編程只讀存儲器 2.5V 1Kb Industrial Temp RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| IS24C01-3GI-TR | 功能描述:電可擦除可編程只讀存儲器 2.5V 1Kb Industrial Temp RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| IS24C01-3GLI | 功能描述:電可擦除可編程只讀存儲器 2.5V 1Kb Industrial Temp RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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